• Title/Summary/Keyword: Common-Gate

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Single chip multi-function peripheral image processor with unified binarization architecture (통합된 이진화 구조를 가진 복합기용 1-Chip 영상처리 프로세서의 개발)

  • Park, Chang-Dae;Lee, Eul-Hwan;Kim, Jae-Ho
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.36S no.11
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    • pp.34-43
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    • 1999
  • A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

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Two Modern Museums in San Francisco: SFMOMA and De Young Museum (San Francisco의 두 현대 미술관, SFMOMA와 De Young Museum)

  • Chung, Jin-Soo
    • Journal of architectural history
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    • v.16 no.4
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    • pp.7-22
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    • 2007
  • In San Francisco, two new museums were recently built in 1995 and 2005. The one is San Francisco Museum of Modern Art designed by Mario Botta and the other is De Young Museum designed by Jacques Herzog & Pierre de Meuron. The urban settings for the museums are compared with each other and theories of the architects are evolved on different branches in the modernist trends. The theories and settings are followed by the representation in the forms, facades, interior spaces and towers. SFMOMA is located on the SoMa area, which was recently developed into a cultural urban core with Moscone Center and Buena Yerba Garden. De Young Museum was rebuilt in the old museum site in the Golden Gate Park. The one is on the context of urban artefacts and the other on the context of natural artefacts. To Botta, the museum in today's city plays a role analogous to that of the cathedral of yesterday. It is a place of common encounter and confrontation. The volume of SFMOMA which is geometrical and symmetric with double pylons. The frontality on the street and public green open space and the axiality of SFMOMA runs through the Buena Yerba Garden over Buena Yerba Center for the Arts are reminded us of an urban core with a religious monument and a city square. The staircase with grandiose design in the atrium seems to work as an altar with lighting from skylight above enhancing the liturgical ambiance. De Young Museum is shaped in a rectangle with long narrow courtyards. Three bands of volumes are juxtaposed and the nature flows into the museum corridors and galleries. The tower is distorted so as to be aligned to the street grids of the surrounding area. The copper panel of De Young Museum and natural context evoke modern concept of "machine in the garden". The two museums from different pedigrees of Modern Architecture are now major landmarks of SF and urban expressions for the 21st century.

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Design of Sub-pixel Interpolation Circuit for Real-time Multi-decoder Supporting 4K-UHD Video Images (4K-UHD 영상을 지원하는 실시간 통합 복호기용 부화소 보간 회로 설계)

  • Lee, Sujung;Cho, Kyeongsoon
    • Journal of IKEEE
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    • v.19 no.1
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    • pp.1-9
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    • 2015
  • This paper proposes the design of sub-pixel interpolation circuit for real-time multi-decoder supporting 4K-UHD video images. The proposed sub-pixel interpolation circuit supports H.264, MPEG-4, VC-1 and new video compression standard HEVC. The common part of the interpolation algorithm used in each video compression standard is shared to reduce the circuit size. An intermediate buffer is effectively used to reduce the circuit size and optimize the performance. The proposed sub-pixel interpolation circuit was synthesised by using 130nm standard cell library. The synthesized gate-level circuit consists of 122,564 gates and processes 35~86 image frames per second for 4K-UHD video at the maximum operation frequency of 200MHz. Therefore, the proposed circuit can process 4K-UHD video in real time.

Effect of Flow-Regime Change due to Damming on the River Morphology and Vegetation Cover in the Downstream River Reach: A case of Hapchon Dam on the Hwang River (댐 건설에 의한 유황 변화에 따른 하류 하도에서 하천지형학적 변화 및 식생피복의 변화: 황강 합천댐 사례)

  • Choi, Sung-Uk;Yoon, Byung-Man;Woo, Hyo-Seop;Cho, Kang-Hyun
    • Journal of Korea Water Resources Association
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    • v.37 no.1
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    • pp.55-66
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    • 2004
  • The Hapchon Dam, located upstream of the Hwang River, Korea, was constructed in December, 1988. Due to the lack of storage of water, the dam gate has not been operated during last ten years. Thus, a new ecosystem has been established at the downstream part of the dam. This is not a common phenomenon which can be found elsewhere in the country. The present study investigates the effect of flow regime change on the river morphology and vegetation cover in the downstream river reach after the dam construction. The analysis of flow regime is carried out, and the changes in bed elevation and in channel cross sections are examined. Site investigations including tree ring tests are also performed. The increase in the vegetation cover is estimated by comparing aerial photographs taken before and after dam construction.

New Semiconducting Multi-branched Conjugated Molecules Bearing 3,4-Ethylene-dioxythiophene-based Thiophenyl Moieties for Organic Field Effect Transistor

  • Kim, Dae-Chul;Lee, Tae-Wan;Lee, Jung-Eun;Kim, Kyung-Hwan;Cho, Min-Ju;Choi, Dong-Hoon;Han, Yoon-Deok;Cho, Mi-Yeon;Joo, Jin-Soo
    • Macromolecular Research
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    • v.17 no.7
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    • pp.491-498
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    • 2009
  • New $\pi$-conjugated multi-branched molecules were synthesized through the Homer-Emmons reaction using alkyl-substituted, 3,4-ethylenedioxythiophene-based, thiophenyl aldehydes and octaethyl benzene-l,2,4,5-tetrayltetrakis(methylene) tetraphosphonate as the core unit; these molecules have all been fully characterized. The two multi-branched conjugated molecules exhibited excellent solubility in common organic solvents and good self-film forming properties. The semiconducting properties of these multi-branched molecules were also evaluated in organic field-effect transistors (OFET). With octyltrichlorosilane (OTS) treatment of the surface of the $SiO_2$ gate insulator, two of the crystalline conjugated molecules, 7 and 8, exhibited carrier mobilities as high as $2.4({\pm}0.5){\times}10^{-3}$ and $1.3({\pm}0.5){\times}10^{-3}cm^2V^{-1}s^{-1}$, respectively. The mobility enhancement of OFET by light irradiation ($\lambda$ = 436 nm) supported the promising photo-controlled switching behavior for the drain current of the device.

Considerations of Automatic Passenger Counting System using Infrared Sensors at doorway in Overseas Railway Transit (적외선 센서를 이용한 자동 승객 계수 시스템에 대한 고찰)

  • Kim, Jin-Seok;Gwak, Ho-Seung
    • Proceedings of the KSR Conference
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    • 2009.05a
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    • pp.418-423
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    • 2009
  • Unlike domestic railway transportation system in which majority of station are equipped with gate access controller and ticket office, it has been a very common practice in overseas railway transit or railway station that they use a pressure door mat, infrared-sensors or CCTV cameras so as to automatically determine the number of passenger onboard and alight and to reflect the information to their business (i.e., deployment of vehicles and human resources). The data collected by the automatic passenger counting (APC) system provides methods how to obtain the information about the number of passenger using the vehicles on the basis of date, time and stop(station) which enables large-scaled transit company to create profits through effective vehicle deployment and management of their employees. This paper addresses the basic features of the automatic passenger counting system using infrared sensor and describes those of the extended APC system in conjunction with wireless technologies such as GPS, WLAN or Cellular network.

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Design of Temperature Compensation Circuit for W-band Radar Receiver (W-band 레이더 수신기용 온도보상회로 설계)

  • Lee, Dongju;Kim, Wansik;Kwon, Jun-Beom;Seo, Mihui;Kim, Sosu
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.4
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    • pp.129-133
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    • 2020
  • In this paper, a temperature compensation circuit is presented in order to mitigate gain variability due to temperature in the W-band low-noise amplifier (LNA). The proposed cascode temperature compensation bias circuit automatically controls gate bias voltages of the common-source LNA in order to suppress variations of small-signal gain. The designed circuit was realized in a 100-nm GaAs pHEMT process. The simulated voltage gain of W-band LNA including the proposed bias circuit is >20 dB with gain variability less than ±0.8 dB in the range of temperatures between -35 to 71℃. We expect that the proposed circuit contributes to millimeter-wave receivers for stable performances in radar applications.

The Flat Structure and Transformation of Southern Royal Villa in Joseon Dynasty (조선시대 남별궁(南別宮)의 평면 구조와 변화)

  • Lee, Jong-Seo
    • Journal of architectural history
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    • v.29 no.1
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    • pp.51-64
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    • 2020
  • Southern Royal Villa served as an accommodation for the prince in early Joseon Dynasty, and as an official residence and banquet room for Chinese diplomats in the later period. It was facing south and was located at the southern part of the old town of Seoul and to the north of the Southern Gate. The place was divided into four parts: the outmost, the middle, the inner-middle and the inner part beginning from the south and with important buildings placed in the inner part. The residence for the first and the second highest diplomats was situated at the northernmost location. The residence for the highest diplomat was a two-story building. On the west side of the residence was the large scale Western Banquet Room. It consisted of a single wide hall suited for a grand ceremony, and had the greatest formality and solemnity. On the southwestern side of the diplomatic residence was a building which was called Momchae before the early 17th century and Namru(南樓) after the 19th century. Namru in the inner-middle part is the half-sized remnant of Momchae, which used to be the largest building in the Southern Royal Villa. The title 'Momchae (meaning Main Buildling)' signifies that the building represented the entire Villa when it was built as an accommodation for princes. The layout of the Villa in early Joseon Dynasty, which was centered around Momchae, is highly likely to have been a common structure of royal villa for princes during the period.

DTMOS Schmitt Trigger Logic Performance Validation Using Standard CMOS Process for EM Immunity Enhancement (범용 CMOS 공정을 사용한 DTMOS 슈미트 트리거 로직의 구현을 통한 EM Immunity 향상 검증)

  • Park, SangHyeok;Kim, SoYoung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.10
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    • pp.917-925
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    • 2016
  • Schmitt Trigger logic is a gate level design method to have hysteresis characteristics to improve noise immunity in digital circuits. Dynamic Threshold voltage MOS(DTMOS) Schmitt trigger circuits can improve noise immunity without adding additional transistors but by controlling substrate bias. The performance of DTMOS Schmitt trigger logic has not been verified yet in standard CMOS process through measurement. In this paper, DTMOS Schmitt trigger logic was implemented and verified using Magna $0.18{\mu}m$ MPW process. DTMOS Schmitt trigger buffer, inverter, NAND, NOR and simple digital logic circuits were made for our verification. Hysteresis characteristics, power consumption, and delay were measured and compared with common CMOS logic gates. EM Immunity enhancement was verified through Direct Power Injection(DPI) noise immunity test method. DTMOS Schmitt trigger logics fabricated using CMOS process showed a significantly improved EM Immunity in 10 M~1 GHz frequency range.

A 6-16 GHz GaN Distributed Power Amplifier MMIC Using Self-bias

  • Park, Hongjong;Lee, Wonho;Jung, Joonho;Choi, Kwangseok;Kim, Jaeduk;Lee, Wangyong;Lee, Changhoon;Kwon, Youngwoo
    • Journal of electromagnetic engineering and science
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    • v.17 no.2
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    • pp.105-107
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    • 2017
  • The self-biasing circuit through a feedback resistor is applied to a gallium nitride (GaN) distributed power amplifier (PA) monolithic microwave circuit (MMIC). The self-biasing circuit is a useful scheme for biasing depletion-mode compound semiconductor devices with a negative gate bias voltage, and is widely used for common source amplifiers. However, the self-biasing circuit is rarely used for PAs, because the large DC power dissipation of the feedback resistor results in the degradation of output power and power efficiency. In this study, the feasibility of applying a self-biasing circuit through a feedback resistor to a GaN PA MMIC is examined by using the high operation voltage of GaN high-electron mobility transistors. The measured results of the proposed GaN PA are the average output power of 41.1 dBm and the average power added efficiency of 12.2% over the 6-16 GHz band.