• Proceedings of the KIPE Conference
• /
• 2016.07a
• /
• pp.487-488
• /
• 2016

In this paper, a new active circuit for common-mode voltage (CMV) cancellation in three-level NPC (neutral-point clamped) inverters is proposed, which can avoid the saturation of the common-mode transformer (CMT). The proposed circuit utilizes an additional three-level leg to produce the compensating CMV of the NPC inverters, which eliminates the CMV of the inverter through the CMT.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.9
• /
• pp.714-723
• /
• 2003

An effective technique to increase the signal swing and reduce noise is to use fully-differential -circuits. However, design of a common-mode feedback (CMFB) circuit that stabilizes the common-mode output level is essential. In this paper, a general description is given to fully-differential amplifiers with their CMFB loops, then a new error amplifier that is just composed of transistors and stabilizes the DC output level is proposed. We designed a simple and efficient bias circuit that allows the stability and maximum input swing. Simulation result shows the enhanced phase margin and increased differential-mode input swing with a proposed error amplifier.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.4 no.4
• /
• pp.2-12
• /
• 1967

A pair of insulated-gate metal-oxide-semiconductor field-effect transistor has been used to measure the direct current produced from the ionization chamber in the range of to A. An analisis of direct-current differential amplifier giving the expressions of the common-mode rejection ratio and the rralization of the constant-current generator to give very large effective source resistance has been presented. Voltage gain is 6.6, drift at the room temperature is 1.5mv per day. The common-mode rejection ratio is obtained maximum 84db. These facts give the feasibility of small direct-current measurements by utilizing this type transistors.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.1406-1407
• /
• 2007

본 논문에서 제안한 ac-PDP(Plasma display panel) 셀구조는 Long gap의 전극 사이에 보조 전극을 삽입한 구조이다. 일반적으로, long gap 구조를 가진 PDP cell은 높은 방전 개시 전압을 가지므로, Long gap 전극 사이에 보조전극을 삽입하여 방전 개시 전압을 낮춤과 동시에 휘도 상승, 소비 전력의 감소효과로 발광효율의 향상을 가져왔다. 제안한 구조의 구동을 위하여 asymmetric mode와 long gap mode라는 2가지 파형을 가지고 실험하였다. 두 파형은 공통적으로 기존의 ADS(Address and Display period Separated)파형을 Y(Scan), Z(Common), A(Address) 전극에 인가하였으며, 보조적극에는 Z(Common) 전극의 파형을 수정한 형태로 인가하였다. Asymmetric mode는 보조전극에 Z(Common) 전극에 인가되는 파형과 같은 형태의 파형을 인가하여 Long gap의 구조를 가지지만 Short gap에서 방전이 가능하도록 설계하였고, long gap mode는 보조전극에 인가되는 Z(Common) 파형 중 sustain pulse를 초기 3개만을 주어 Short gap에서 방전을 개시함과 동시에 priming 입자를 생성하고, 나머지 sustain 구간에서는 floating시켜 이미 생성된 priming 입자를 long gap에서 구동을 가능하도록 하였다.

• The Journal of the Korea Contents Association
• /
• v.6 no.3
• /
• pp.38-45
• /
• 2006

A dual-level low voltage differential signalling (DLVDS) circuit is proposed aiming at reducing transmission lines for a LCD driver IC. We apply two data to the proposed DLVDS circuit as inputs. Then, the transmitter converts two inputs to two kinds of fully differential signals. In this circuit, two transmission lines are sufficient to transfer two inputs while keeping the LVDS feature. However, the circuit has a common mode bias fluctuation due to difference of the input bias and the reference bias. We compensate the common mode bias fluctuation using a feedback circuit of the current source bias. The receiver recovers the original input data through a level decoding circuit. We fabricated the proposed circuit using $0.25{\mu}m$ CMOS technology. The simulation results of proposed circuit shows 1-Gbps/2-line data rate and 35mW power consumption at 2.5V supply voltage, respectively.

• Proceedings of the KIEE Conference
• /
• summer
• /
• pp.1232-1234
• /
• 2004

In this paper, we represent both occurrence reason of Surge-voltage and Leakage current of AC drive system which is operated by Voltage-type PWM Inverter. It generates a compensating voltage which has the same amplitude as, but the opposite phase to, the common-mode voltage produced by the PWM inverter. The compensating voltage is superimposed on the inverter output by a common-mode transformer. As a result, the common-mode voltage applied to the load is canceled completely. The design method of the active common-mode noise canceler is also presented in detail. Therefore, we try to describe the method controling both of them and all of the proprieties are proved by our experiment.

• Proceedings of the KIPE Conference
• /
• 2019.07a
• /
• pp.384-385
• /
• 2019

본 논문에서는 단상 컨버터/3상 인버터 시스템에서 공통모드 전압 저감을 위한 PWM 기법을 제안한다. 컨버터/인버터 시스템은 스위칭에 의한 공통모드 전압으로 인해 전동기의 누설전류와 절연파괴 등의 문제가 발생할 수 있다. 이에 본 논문에서는 영전압벡터 인가시간에 따라 유효전압벡터의 위치를 선정하여 공통모드 전압을 저감하는 방법에 대해 제안한다. 모의실험을 통하여 제안된 기법의 효용성을 검증하였다.

• Journal of the Korean Society for Railway
• /
• v.11 no.3
• /
• pp.248-256
• /
• 2008

The study aims at verifying no generation of electrical power induced noise voltage on telecommunications lineside cable by analyzing the practical findings of noise voltage produced at the telecommunication lines in the vicinity of electrified high-speed railways like KTX, while proposing to make the current standard measurement circuit along with its measuring conditions revised in compliance with international ITU-T recommendations by identifiably finding out the present problems in balance level measuring instruments as well as their errors in the measurement method now applicable by local telecommunications companies and the Radio Research Laboratory.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.19 no.6
• /
• pp.488-493
• /
• 2014

This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

• Proceedings of the KIPE Conference
• /
• 2020.08a
• /
• pp.106-108
• /
• 2020

This paper introduces a new pulse-width modulation (PWM) method to reduce common-mode voltages (CMVs) and compare its performance with other reduced CMV-PWM (RCMV-PWM) methods. To avoid the use of zero-vectors which cause high CMV peaks, the introduced method splits every reference vector into two vectors such that the peak-to-peak magnitude of CMV is reduced by one-third of conventional space-vector PWM (SVPWM). The performance of RCMV-PWMs altered by the modulation index are analyzed with simulation results.