• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.893-898
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• 2017

A TDC(Time-to-Digital Converter) of counter-type is designed by $0.18{\mu}mCMOS$process and the supply voltage is 1.5 volts. The converted error of maximum $T_{CK}$ is occurred by the time difference between the start signal and the clock when the period of clock is $T_{CK}$ in the conventional TDC. And the converted error of -$T_{CK}$ is occurred by the time difference between the stop signal and the clock. However in order to compensate the disadvantage of the conventional TDC the clock is generated within the TDC circuit and the clock is synchronized with the start and stop signals. In the designed TDC circuit the conversion error is not occurred by the difference between the start signal and the click and the magnitude of conversion error is reduced (1/2)$T_{CK}$ by the time difference between the stop signal and the clock.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.338-347
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• 1989

In this paper, the digital frequency synthesizer with the clock ccunting method is designed and implemented to increase the performace of the digital frequency synthesizer with pahse accumulating method which was developed before. Unlike an phase accumulating method, clock countind method is supplied a continually changeable clock frequency with PLL(Phase Locked Loop) and allocated a fixed phase step with N-ary counter. Form the experimenta results, it is confirmed that any periodic distorition phenomena are disappeared, and truncation harmonics are more reduced. But the output bandwidths are decreased in inverse proportion to the counter counting number and the circuits are somewhat complex than phase accumulating method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.520-521
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• 2017

The converted error is occurred by the time difference between the time interval signal and the clock in a Time-to-Digital Converter of counter-type. If the clock period is $T_{CLOCK}$ the converted error is a maximum $T_{CLOCK}$ by the time difference between the start signal and the clock. And the converted error is a maximum $-T_{CLOCK}$ by the time difference between the stop signal and the clock. However, when the clock is synchronized with the start signal and the colck is generated during the time interval signal the range of converted digital error is from 0 to $(1/2)T_{CLOCK}$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.7
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• pp.885-890
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• 2020

In the distance measurement system the time-to-digital conversion circuit used measures the distance using the time interval between the start signal and the stop signal. The time interval is generally converted to digital information using a counter circuit considering the response speed. Therefore, a clock signal with a high frequency is required to improve precision, and a clock signal with a high frequency is also required to measure fine distances. In this paper, a counter circuit was designed to increase the accuracy of distance measurement while using the same frequency. The circuit design was performed using a 0.18㎛ CMOS process technology, and the operation of the designed circuit was confirmed through HSPICE simulation. As a result of the simulation, it is possible to obtain an improvement of four times the precision compared to the case of using a general counter circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.577-582
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• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• The KIPS Transactions:PartC
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• v.18C no.1
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• pp.7-14
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• 2011

Power analysis attack on low-power consumed security devices such as smart cards is very powerful, but it is required that the correlation between the measured power signal and the mid-term estimated signal should be consistent in a time instant while running encryption algorithm. The power signals measured from the security device applying the random clock do not match the timing point of analysis, therefore random clock is used as counter measures against power analysis attacks. This paper propose a new constant pitch based time alignment for power analysis with random clock power trace. The proposed method neutralize the effects of random clock used to counter measure by aligning the irregular power signals with the time location and size using the constant pitch. Finally, we apply the proposed one to AES algorithm within randomly clocked environments to evaluate our method.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.404-409
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• 2014

This paper presents a Spread Spectrum Clock Generator (SSCG) based on Relaxation oscillator using Up/Down Counter. The current is controlled by a counter and the spread spectrum of the Relaxation Oscillator. A Relaxation Oscillator with temperature compensation using the BGR and ADC is presented. The current to determine the frequency of the Relaxation Oscillator can be controlled. The output frequency of the temperature can be compensated by adjusting the current according to the temperature using the code that is the output from the ADC and BGR. EMI Reduction of SSCG is 11 dB, and Spread down frequency is 150 kHz. The current consumption is $600{\mu}A$ from 5V and the operating frequency is from 2.3 MHz to 5.75 MHz. The rate of change of the output frequency with temperature was approximately ${\pm}1%$. The SSCG is fabricated in a 0.35um CMOS process with active area $250um{\times}440um$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2113-2120
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• 2009

User authentication has been one of the most important part of the network system. OTP(One-Time Password) has been developed and applied to the existing authentication system. OTP makes a different password and abrogates used password each time when user is authenticated by the server. Those systems prevent stolen-key-problems which is caused by using the same key every log-in trial. Yet, OTP still has vulnerabilities. In this paper, an advanced protocol which is using clock-count method to apply a stream cipher algorithm to OTP protocols and to solve problems of existing OTP protocols is proposed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.79-85
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• 2004

A digitally-controlled analog-block inevitably undergoes the bang-bang oscillations which may cause a big amplitudes of the glitches if the oscillation occurs at the MSB transition points of a binary counter. The glitch results into the jitter noise for the case of the DLL. In this paper, we devise a new counter code that has the hysteresis in the bit transitions in order to prevent the transitions of the significant counter-bits at the locking state. The maximum clock jitter is simulated to considerably reduce over the voltage-temperature range guaranteed by specifications. The counter is employed to implement the high speed packet-base DRAM and contributes to the maximized valid data-window.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.106-109
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• 2004

In this project, we have developed the eye-safe LRF system of 1.54 ${\mu}{\textrm}{m}$ wavelength using OPO. The maximum measured distance was 3.7km in outdoor experiment. We used Nd：YAG (1064nm) as a laser medium. It was applied BBO to construct the system. We also developed a time-counter for the range finder using a method of TOF (time of flight). The counter-clock used at the time counter was 320MHz making resolution within $\pm$1m. Start and stop signals were detected by two channel systems using PIN and APD. The LRF's repetition rate was 4 times per minute. The energy was measured to be over 9mJ. And, pulse-duration was 23ns. Resolution was $\pm$2m at the distance measurement using a target.