• Proceedings of the KIEE Conference
• /
• 2004.11c
• /
• pp.391-393
• /
• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.1
• /
• pp.11-22
• /
• 2016

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period ($T_{clk}$) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.3
• /
• pp.232-239
• /
• 2010

By using the clock timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). Compared to the authors' prior work, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The delay block generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a $0.18\;{\mu}m$ CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors' prior work, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2004.05b
• /
• pp.583-586
• /
• 2004

In this paper, we have analyzed the performance of synchronization of CCK(Complementary Code Keying) modulation scheme used for IEEE 802.11g wireless LAM system supporting 54 Mbps of high speed data rate over 2.4 GHz. At receiver, the clock frequency offset is caused by noise or fading. This frequency error occurs the offset of clock timing and causes ISI. Therefore the tracking is required to reduce the clock timing offset. The DLL(Delay Lock Loop), asychronization mode, performing tacking the clock is used for the simulation. The simulation result shows jitter variance and BER performance in the AWGN and multipath fading channel environment.

• Journal of Positioning, Navigation, and Timing
• /
• v.5 no.3
• /
• pp.137-144
• /
• 2016

In this paper, the performance of ranging measurement, which is generated using two receiver clock offsets in one receiver, was analyzed. A spoofer transmits a counterfeited spoofing signal which is similar to the GPS signal with hostile purposes, so the same tracking technique can be applied to the spoofing signal. The multi-correlator can generate two receiver clock offsets in one receiver. The difference between these two clock offsets consists of the path length from the spoofer to the receiver and the delay of spoofer system. Thus, in this paper, the ranging measurement was evaluated by the spoofer localization performance based on the time-of-arrival (TOA) technique. The results of simulation and real-world experiments show that the position and the system clock offset of the spoofer could be estimated successfully.

• Journal of Positioning, Navigation, and Timing
• /
• v.8 no.4
• /
• pp.209-214
• /
• 2019

Precise point positioning (PPP) requires precise orbit and clock products. International GNSS service (IGS) real-time service (RTS) data can be used in real-time for PPP, but it may not be possible to receive these corrections for a short time due to internet or hardware failure. In addition, the time required for IGS to combine RTS data from each analysis center results in a delay of about 30 seconds for the RTS data. Short-term orbit prediction can be possible because it includes the rate of correction, but the clock correction only provides bias. Thus, a short-term prediction model is needed to preidict RTS clock corrections. In this paper, we used a long short-term memory (LSTM) network to predict RTS clock correction for three minutes. The prediction accuracy of the LSTM was compared with that of the polynomial model. After applying the predicted clock corrections to the broadcast ephemeris, we performed PPP and analyzed the positioning accuracy. The LSTM network predicted the clock correction within 2 cm error, and the PPP accuracy is almost the same as received RTS data.

• Journal of Communications and Networks
• /
• v.18 no.1
• /
• pp.65-74
• /
• 2016

Ship ad-hoc network (SANET) extends the coverage of the maritime communication among ships with the reduced cost. To fulfill the growing demands of real-time services, the SANET requires an efficient clock time synchronization algorithm which has not been carefully investigated under the ad-hoc maritime environment. This is mainly because the conventional algorithms only suggest to decrease the beacon collision probability that diminishes the clock drift among the units. However, the SANET is a very large-scale network in terms of geographic scope, e.g., with 100 km coverage. The key factor to affect the synchronization performance is the signal propagation delay, which has not being carefully considered in the existing algorithms. Therefore, it requires a robust multi-hop synchronization algorithm to support the communication among hundreds of the ships under the maritime environment. The proposed algorithm has to face and overcome several challenges, i.e., physical clock, e.g., coordinated universal time (UTC)/global positioning system (GPS) unavailable due to the atrocious weather, network link stability, and large propagation delay in the SANET. In this paper, we propose a logical clock synchronization algorithm with multi-hop function for the SANET, namely multi-hop clock synchronization for SANET (MCSS). It works in an ad-hoc manner in case of no UTC/GPS being available, and the multi-hop function makes sure the link stability of the network. For the proposed MCSS, the synchronization time reference nodes (STRNs) are efficiently selected by considering the propagation delay, and the beacon collision can be decreased by the combination of adaptive timing synchronization procedure (ATSP) with the proposed STRN selection procedure. Based on the simulation results, we finalize the multi-hop frame structure of the SANET by considering the clock synchronization, where the physical layer parameters are contrived to meet the requirements of target applications.

• Korean Journal of Optics and Photonics
• /
• v.17 no.1
• /
• pp.68-74
• /
• 2006

We have extracted an optical clock signal from a return-to-zero(RZ) pseudorandom bit sequence(PRBS) and non-return-to-zero(NRZ) PRBS data in a pulsation multi-section laser diode with DFB reflector. The ms timing jitter achieved less than 1 ps for the input 11.727 Gbit/s RZ PRBS and NRZ PRBS data. The PRE data wasconverted from the NRZ data using an NRZ to pseudo-return to zero(PRZ) converter module. The optical clock was extracted from the PRZ data which contains the clock components. Although the input PRZ data gives a timing jitter of 2 ps, the extracted clock has timing jitter of ${\~}$1 ps.

• Journal of IKEEE
• /
• v.3 no.1 s.4
• /
• pp.50-56
• /
• 1999

This paper presents a new technique for generating precise clock delays. The technique can obtain finer timing resolution less than the gate delay of the delay chain by locking in multiple clock period. Using this technique, a 250ps of timing resolution could be achieved from a 750ps delay of the single delay stage in a DLL(Delay Locked Loop) structure. The delay chain of the proposed circuit is locked on three times of the clock period and a finer delay resolution than the absolute gate delay is achieved and verified through the simulation.

• Journal of Positioning, Navigation, and Timing
• /
• v.5 no.3
• /
• pp.157-163
• /
• 2016

Clocks for time synchronization using radio signals such as global navigation satellite system (GNSS) may lose reference signals by intentional or unintentional jamming. This is called as holdover. When holdover occurs, a clock goes into free run in which synchronization performance is degraded considerably. In order to maintain the required precise time synchronization during holdover, accurate estimation on main parameters such as frequency offset and frequency drift is needed. It is necessary to implement an optimum filter through various simulation tests by creating clock noise in accordance with given specifications in order to estimate the main parameters accurately. In this paper, a method that creates clock noise in accordance with given specifications is described.