• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• The Journal of the Acoustical Society of Korea
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• v.18 no.2
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• pp.53-60
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• 1999

In this paper, it is proposed to a new architecture of CMOS IADC(Current-Mode Analog-to-Digital Converter) using 1.5-bit bit cell of which consists a CSH(Current-Mode Sample-and-Hold) and CCMP(Current-Mode Comparator). In order to guarantee the entire linearity of IADC, the CSH is designed to cancel CFT(Clock Feedthrough) whose resolution is to meet at the least 9-bit which is placed in the front-end of each bit cell. In the proposed IADC, digital correction logic is simplified and power consumption is reduced because bit cell of each stage needs two latch CCMP. Also, it is available for a mixed-mode integrated circuit because all of block is designed with only MOS transistor. With the HYUNDAI 0.8㎛ CMOS parameter, the HSPICE simulation results show that the proposed IADC can be operated at 20Ms/s with SNR of 43 dB with which is satisfied 7-bit resolution for input signal at 100 ㎑, and its power consumption is 27㎽.

• Journal of Arbitration Studies
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• v.20 no.3
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• pp.121-145
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• 2010

In the past, ADR has not been used as frequently in Japan as it has in other parts of the industrialized world. However, though litigation is still the most utilized vehicle of dispute resolution by Japanese financial institutions, this will be changing. The New Financial ADR system, which was created by a June 2009 amendment to the Financial Instruments and Exchange Act, is meant to deal with every stage of financial-related disputes and, as such, strives to resolve disputes before they become significant and acts to ameliorate any post-ADR issues that may remain, thereby completing the FIEA's purpose to protect investors. Since the foundation of the New Financial ADR system applies to all related industries, new provisions were set out in 16 business related acts, such as the Banking Act, the Insurance Business Act, and FIEA itself. October 2010 will mark the formal introduction of a new system of financial ADR in Japan. New Financial ADR in Japan will be modeled on the Financial Ombudsman Service in the United Kingdom, but will not feature one comprehensive dispute resolution system in which one dispute resolution institution covers all disputes in the financial field. The New Financial ADR system is merely one step towards a foundation of comprehensive financial ADR such as FOS. It must be noted, however, that this all important first step was over seven years in the making, involving a great deal of discussion, debate, and compromise amongst many parts of Japanese government, business, and society. The New Financial ADR system grants participating parties the ability to stop the clock on any statute of limitations which may correspond to any future possible court cases related to the dispute,13 and further grants the ability to suspend related court proceedings while the parties are utilizing the New Financial ADR system. In addition, where financial institutions have not accepted dispute resolution proceedings or have not accepted a special conciliation proposal, the Ministry of Finance may issue an order compelling compliance if it is found that certain actions are necessary to ensure the appropriate operations of a financial institution's business. In Japan, as best practices have not yet been created.

• Journal of Korean Academy of Nursing Administration
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• v.20 no.5
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• pp.535-544
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• 2014

Purpose: This study was done to develop a schematized alarm-managing manual for continuous renal replacement therapy (CRRT) and to investigate its effects in maintaining continuity in the patients' treatment and promptly resolving alarms when CRRT is being carried out. Methods: Sixtynurses from two medical intensive care units (ICUs) (one experimental and one control) at one hospital were asked to answer a questionnaire including their CRRT nursing competency and satisfaction with the manual. Data on alarm resolution rate were collected by analyzing existing data, such as the details of each alarm and the number of resolutions around the clock in the CRRT device. Results: The alarm resolution rate and some of CRRT nursing competency scores in the experimental group were higher than those in the control group. The experimental group was also satisfied with the manual. Conclusion: The study confirmed that the schematized alarm-managing manual can be useful for ICU nurses to resolve alarms and can be used as a guideline. Application of this manual to clinical practices and its use can therefore, be encouraged through continuous education and promotion.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1666-1671
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• 1989

A novel switched-capacitor circuit for interfacing capacitive microtransducers with a digital system is developed based on the dual-slope integration. It consists of a differential integrator and a comparator. Driven by the teo phase clock, the circuit first senses the capacitance difference between the transducer and the reference capacitor in the form of charge, and accumulates it into the feedback capabitor of the integrator for a fixed period of time. The resulant accumulated charge is next extracted by the known reference charge until the integrator output voltage refurns to zero. The length of time required for the integrator output to return to zero, as measured by the number of clock cycle gated into a counter is proportional to the capacitance difference, averaged over the integration period. The whole operation is insensitive to the reference voltage and the capacitor values involved in the circuit, Thus the proposed circuit permits an accurate differental capacitance measurement. An error analysis has showh that the resolution as high as 8 bits can be expected by realizing the circuit in a monolithic MOS IC form. Besides the accuracy, it features the small device count integrable onto a small chip area. The circuit is thus particularly suitadble for the on-chip interface.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.10-17
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• 1999

In this paper, CMOS IADC(Current-mode Analog-to-Digital Converter) which consists of only CMOS transistors is proposed. Each stages is made up 1.5-bit bit cells composed of CSH(Current-mode Sample-and-Hold) and CCMP(Current Comparator). The differential CSH which designed to eliminate CFT(Clock Feedthrough), to meet at least 9-bit resolution, is placed at the front-end of each bit cells, and each stages of bit cell ADSC (Analog-to-Digital Subconverter) is made up two latch CCMPs. With the HYUNDAI TEX>$0.65\mu\textrm{m}$ CMOS parameter, the ACAD simulation results show that the proposed IADC can be operated with 47 dB of SINAD(Signal to Noise- Plus-Distortion), 50dB(8-bit) of SNR(Signal-to-Noise) and 37.7 mW of power consumption for input signal of 100 KHz at 20 Ms/s.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.152-161
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• 1996

In tis work, a three-stage pipelined A/D converter (ADC) was implemented to obtain 10-bit resolution at a conversion rate of 20 msamples/s for video applications. The ADC consists of three identical stages employing a mid-rise coding technique. The interstage errors such as offsets and clock feedthrough are digitally corrected in digitral logic by one overlapped bit between stages. The proposed ADC is optimized by adopting a unit-capacitor array architecture in the MDAC to improve the differential nonlinearity and the yield. Reduced power dissipation has been achieve dby using low-power latched comparators. The prototype was fabricated in a 0.8$\mu$m p-well CMOS technology. The ADC dissipates 160 mW at a 20 MHz clock rate with a 5 V single supply voltage and occupies a die area of 7 mm$^{2}$(2.7 mm $\times$ 2.6mm) including bonding pads and stand-alone internal bias circuit. The typical differential and integral nonlinarities of the prototype are less than $\pm$ 0.6 LSB and $\pm$ 1 LSB, respectively.

• Journal of Sensor Science and Technology
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• v.24 no.6
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• pp.359-363
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• 2015

This paper proposes an algorithm that reduces the conversion time of a single-slope A/D converter (SSADC) that has n-bit resolution, which typically is limited by conversion time taking up to $2^n$ clock cycles for an operation. To improve this situation, we have researched a novel hybrid-type A/D converter that consists of a pseudo-pipeline A/D converter and a conventional SSADC. The pseudo-pipeline A/D converter, using a single-stage of analog components, determines the most significant bits (MSBs) or upper bits and the conventional SSADC determines the remaining bits. Therefore, the modified SSADC, similar to the hybrid-type A/D converter, is able to significantly reduce the conversion time because the pseudo-pipeline A/D converter, which determines the MSBs (or upper bits), does not rely on a clock. The proposed A/D converter was designed using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) technology process; additionally, its characteristics were simulated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1983-1993
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• 1993

A power-reduction technique for full-flash A/D converters is proposed. As the resolution of a full-flash A/D converter increases linearly, the number of comparators increases exponentially. The power dissipation is generally larger than other A/D converter architectures because there are many comparators, and they are operating continuously. In this proposed architecture, only a selected number of conmarators are made to operate instead of activating all the comparators of the full-flash A/D convertor. To determine whichcomparators should be activated, voltage levelfider circuits are used. A new clock driver is developed to suppress the dynamic glitch noise which is fed back into the input stage of the comparator. By using this clock driver, the glitch noise in the current source is reduced to one fourth of that when the typical clock signal is applied. The proposed architecture has been implemented with 1.2 m 5GHz BiCMOS technology. The maximum conversion speed is 350Msamples/s. and dissipates only 900mW.