• Journal of Positioning, Navigation, and Timing
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• v.11 no.4
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• pp.269-277
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• 2022

In this paper, we overview the system development status of the national maritime precise point positioning-real-time kinematic (PPP-RTK) service in Korea, also known as the Precise POsitioning and INTegrity monitoring (POINT) system. The development of the POINT service began in 2020, and the open service is scheduled to start in 2025. The architecture of the POINT system is composed of three provider-side facilities-a reference station, monitoring station, and central control station-and one user-side receiver platform. Here, we propose the detailed functionality of each component considering unidirectional broadcasting of augmentation data. To meet the centimeter-level user positioning accuracy in maritime coverage, new reference stations were installed. Each reference station operates with a dual receiver and dual antenna to reduce the risk of malfunctioning, which can deteriorate the availability of the POINT service. The initial experimental results of a testbed from corrections generated from the testbed network, including newly installed reference stations, are presented. The results show that the horizontal and vertical accuracies satisfy 2.63 cm and 5.77 cm, respectively. For the purpose of (near) real-time broadcasting of POINT correction data, we designed a correction message format including satellite orbit, satellite clock, satellite signal bias, ionospheric delay, tropospheric delay, and coordinate transformation parameters. The (near) real-time experimental setup utilizing (near) real-time processing of testbed network data and the designed message format are proposed for future testing and verification of the system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.1-9
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• 2009

In this paper, a small area 12-bit 300MSPS CMOS Digital-to-Analog Converter(DAC) is proposed for display systems. The architecture of the DAC is based on a current steering 6+6 segmented type, which reduces non-linearity error and other secondary effects. In order to improve the linearity and glitch noise, an analog current cell using monitoring bias circuit is designed. For the purpose of reducing chip area and power dissipation, furthermore, a noble self-clocked switching logic is proposed. To verify the performance, it is fabricated with $0.13{\mu}m$ thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is $0.26mm^2$ ($510{\mu}m{\times}510{\mu}m$) with 100mW power consumption. The measured INL (Integrated Non Linearity) and DNL (Differential Non Linearity) are within ${\pm}3LSB$ and ${\pm}1LSB$, respectively. The measured SFDR is about 70dB, when the input frequency is 15MHz at 300MHz clock frequency.

• Journal of Korea Water Resources Association
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• v.44 no.12
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• pp.991-1000
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• 2011

The relationship between discharge (Q) and suspended sediment (SS) concentration often is used for the estimation of inflow SS concentration in reservoir turbidity modeling in the absence of actual measurements. The power function, SS=aQb, is the most commonly used empirical relation to determine the SS load assuming the SS flux is controlled by variations of discharge. However, Q-SS relation typically is site specific and can vary depending on the season of the year. In addition, the relation sometimes shows hysteresis during rising limb and falling limb for an event hydrograph. The objective of this study was to examine the hysteresis of Q-SS relationships through continuous field measurements during flood events at inflow rivers of Yongdam Reservoir and Soyang Reservoir, and to analyze its effect on the bias of SS load estimation. The results confirmed that Q-SS relations display a high degree of scatter and clock-wise hysteresis during flood events, and higher SS concentrations were observed during rising limb than falling limb at the same discharge. The hysteresis caused significant bias and underestimation of SS loading to the reservoirs when the power function is used, which is important consideration in turbidity modeling for the reservoirs. As an alternative of Q-SS relation, turbidity-SS relation is suggested. The turbidity-SS relations showed less variations and dramatically reduced the bias with observed SS loading. Therefore, a real-time monitoring of inflow turbidity is necessary to better estimate of SS influx to the reservoirs and enhance the reliability of reservoir turbidity modeling.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1235-1242
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• 2008

In this paper, x-ray image sensor of photon counting type having a $32{\times}32$ pixel array is designed with $0.18{\mu}m$ triple-well CMOS process. Each pixel of the designed image sensor has an area of loot $100{\times}100\;{\mu}m2$ and is composed of about 400 transistors. It has an open pad of an area of $50{\times}50{\mu}m2$ of CSA(charge Sensitive Amplifier) with x-ray detector through a bump bonding. To reduce layout size, self-biased folded cascode CMOS OP amp is used instead of folded cascode OP amp with voltage bias circuit at each single-pixel CSA, and 15-bit LFSR(Linear Feedback Shift Register) counter clock generator is proposed to remove short pulse which occurs from the clock before and after it enters the counting mode. And it is designed that sensor data can be read out of the sensor column by column using a column address decoder to reduce the maximum current of the CMOS x-ray image sensor in the readout mode.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.4
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• pp.43-52
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• 2004

In this paper, the performance of the KOMPSAT-1 orbit determination (OD) accuracy at the ground station was analyzed by using the flight data. The Bayesian least squares estimation was used for the orbit determination and the assessment of the orbit accuracy was evaluated based on orbit overlap comparisons. We also compared the result from OD using GPS navigation solutions with NORAD TLE and the result from OD using range data. Furthermore, the effect of observation type and OBT drift on the accuracy was investigated. As a consequence, It is shown that the OD accuracy using only GPS position data is on the order of 5m RMS (Root Mean Square) with 4 hrs arc overlap for the 30hr arc and the GPS velocity data is not proper as a observation for the OD due to its inferior quality. The significant deterioration of the accuracy due to the critical clock bias was not founded by means of the comparison of OD result from other observations.

• Journal of Astronomy and Space Sciences
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• v.25 no.4
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• pp.481-490
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• 2008

Reaction wheel is one of the actuators for spacecraft attitude control, which generates torque by changing an inertial rotor speed inside of the wheel. In order to generate required torque accurately and estimate an accurate angular momentum, wheel speed should be measured as close to the actual speed as possible. In this study, two conventional speed detection methods for high speed motor with digital tacho pulse (Elapsed-time method and Pulse-count method) and their resolutions are analyzed. For satellite attitude maneuvering and control, reaction wheel shall be operated in bi directional and low speed operation is sometimes needed for emergency case. Thus the bias error at low speed with constant acceleration (or deceleration) is also analysed. As a result, the speed detection error of elapsed-time method is largely influenced upon the high-speed clock frequency at high speed and largely effected on the number of tacho pulses used in elapsed time calculation at low speed, respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.65-73
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• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.