• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.363-376
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• 1997

In this paper, we present a hardware architecture and a sofrware architecture for cimputer based teleconferencing systems.And also we analyse stream adtivation mechanisms for them form the viewpoint of delay. MuX that is a multimedia I/O server provides various processing elements for data I/O, synchronization, interleaving and mixing.We describe methods to build teleconferencing systems with the elements and compares the technique using master click with the techniquie using self clock.In the plase of dta input.the technique using self click is berrer than the technique using master clock.When we generate interleved stream from audio and video stream and activate channel objects by periodic audio stream as activation clock, dealy from imput audio stream to imterleved stream is reduced but delay for video stream is not reduced as much as in the case of audio stream.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.2
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• pp.145-158
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• 1997

Method for synchronizing multimedia data is needed to support continuous transmission of multimedia data through a network in a bounded time and it also required for supporting continuous presentation of multimedia data with the required norminal playout rate in distributed network environments. This paper describes a new synchronization method for supporting delay-sensitive multimedia Presentation without degration of Quality of services of multimedia application. It mainly aims to support both intermedia and intermedia synchronization by absorbing network variations which may cause skew or jitter. In order to remove asynchonization problems, we make use of logical time system, dynamic buffer control method, and adjusting synchronization intervals based on the quality of services of a multimedia. It might be more suitable for working on distribute[1 multimedia systems where the network delay variation is changed from time to time and no global clock is supported. And it also can effectively reduce the amount of buffer requirements needed for transfering multimedia data between source and destination system by adjusting synchronization intervals with acceptable packet delay limits and packet loss rates.

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.121-124
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• 2000

Goal of this Paper is to design and develop core kernel components f3r single processor real-time system, which include real-time schedulers, synchronization mechanism, IPC, message passing, and clock & timer. The goal also contains the basic researches on dynamic load balancing and scheduling which provide mechanism for the distributed information processing and efficient resource sharing among various information appliances based on network.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06a
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• pp.179-180
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• 2008

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.716-719
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• 1999

In this paper, a real-time control system for robot manipulator is implemented using real-time operating system with capabilities of multitasking, intertask communication and synchronization, event-driven, priority-driven scheduling, real-time clock control, etc. The hardware system with VME bus and related devices is developed and applied to implement a dynamic learning control scheme for robot manipulator. Real-time performance of the proposed dynamic learning controller is tested for tasks of tracking moving objects and compared with the conventional servo controller.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11b
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• pp.1085-1088
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• 2003

동기식 전송망에서는 다양한 동기클럭 성능과 상태가 나타날 수 있고, 이는 전송성능에 영향을 줄 수 있기 때문에 전송망 설계에 필요한 최대노드수의 변화가 생길 수 있다. 이에 따라 전송망에서 다양한 클럭성능과 상태를 적용할 수 있는 시뮬레이터가 요구된다. 따라서 본 논문에서는 전송망 동기클럭 시뮬레이터를 살펴보고, 또한 이를 이용하여 NE 노드에 따른 동기클럭 특성과 최대 노드수 결과를 얻었다. 본 연구 결과를 통해 볼 때 NE 노드의 성능보다 동기원의 성능이 최대 노드수에 미치는 영향이 크다는 것은 알 수 있었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.451-452
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• 2009

IEEE 1588은 대칭 망에서만 정확한 클럭 동기화를 제공하는 문제점이 있다. 이를 해결하기 위해 Enhanced IEEE 1588이 제안되었지만, 단순히 비대칭 링크 율만을 고려했다는 한계를 가진다. 본 논문에서는 비대칭 율이 매우 크며 클럭 동기화 정확성에 영향을 미칠 수 있는 요소를 사용한 비대칭 망 환경에서도 정확한 클럭 동기화를 제공할 수 있는 새로운 알고리즘을 제안한다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.9
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• pp.13-19
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• 2008

Time synchronization of nodes in sensor network synchronizes sensor nodes to one time clock. This is very essential in sensor networks so that the information collected and reported from the sensor nodes becomes meaningful. If sensor nodes are not synchronized, disaster report with time information can be wrong analyzed and this may lead to big calamity. With the limitation of battery and computing power, time synchronization algorithm imported in sensor nodes has to be as simple as it doesn't need big complexity, nor generates many synchronization messages. To reduce the synchronization error, hop count should be kept small between reference node to initiate synchronization and sensor nodes to be synchronized. Therefore, multiple reference nodes are used instead of single reference node. The use of multiple reference nodes introduce the requirement of synchronization among reference nodes in the network. Several algorithms have been proposed till now, but the synchronization among reference nodes are not well considered. This paper proposes improved time synchronization for sensor networks by synchronizing multiple reference nodes inside the network. Through simulation, we validated the effects of new algorithm.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.3
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• pp.896-905
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• 2010

The sensor networks can be used attractively for various application areas. Time synchronization is important for any Ubiquitous Sensor Networks (USN) systems. USN makes extensive use of synchronized time in many contexts for data fusion. However existing time synchronization protocols are available only for homogeneous sensor nodes of USN. It needs to be extended or redesigned in order to apply to the USN with heterogeneous sensor nodes. Because heterogeneous sensor nodes have different clock sources with the SinkNode of USN, it is impossible to be synchronized global time. In addition, energy efficiency is one of the most significant factors to influence the design of sensor networks, as sensor nodes are limited in power, computational capacity, and memory. In this paper, we propose specific time synchronization based on master-slave topology for the global time synchronization of USN with heterogeneous sensor nodes. The time synchronization master nodes are always able to be synchronized with the SinkNode. Then time synchronization master nodes enable time synchronization slave nodes to be synchronized sleep periods. The proposed master-slave time synchronization for heterogeneous sensor nodes of USN is also helpful for power saving by maintaining maximum sleep time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1814-1823
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• 2016

LVC(live-virtual-constructive) integrated training system is a representative cyber-physical system. Each systems in a LVC system has different time domain, resolution and operation methods. So, it is very important to integrate different middlewares as a common middleware for heterogeneous systems using inter-working GWs. Especially, since the LVC system uses different time, it is necessary to study the method for guaranteeing causality and time synchronization among the events from different systems. In this study, we propose an time synchronization scheme to integrate the virtual and constructive system which use the simulation time of HLA (High Level Architecture)/ RTI (Run Time Infrastructure) into the live system based on the OMG DDS (Data Distribution Service). We propose a precise time synchronization scheme based on HLA time management and clock federate between participants and federates which are the communication objects of DDS and HLA/RTI respectively. In addition, we verified that time is well-synchronized among heterogeneous systems using the suggested scheme by implementing and demonstrating simulation applications on each middleware.