• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.661-662
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• 2006

This paper introduces a CMOS clock driver that shows a high efficiency of electric power (lower power consumption) with the supply of lower voltage(VDD), by taking advantage of charge recycling technology. Comparing with the existing structure, this driver showed the improved maximum efficiency of electric power; 72% and 68%, with the supplied voltage of 1.8v and 1.2v, respectively. Since the output waveform shows the tri-state operating region, utilization is expected in the digital integrated circuits.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.25 no.6_1
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• pp.537-543
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• 2007

Since the GPS absolute positioning with pseudorange measurements can significantly be affected by the observation error, the time series analysis of the GPS receiver clock errors was performed in this study. From the estimated receiver clock errors, the time series model is generated, and constrained back in the absolute positioning process. One of the CORS (Continuously Operating Reference Stations) network is used to analyze the behavior of the receiver clock. The dominant part of the model is the linear trend during 24 hours, and the seasonal component is also estimated. After constraining the modeled receiver clock errors, the estimated position error compared to the published coordinates is improved from ${\pm}11.4\;m\;to\;{\pm}9.5\;m$ in 3D RMS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.2
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• pp.193-197
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• 1997

In this paper, we propose a new PN chip clock generator which employs two synchronous counters to achieve precise phase control of chip clock. In a CDMA code acquisition and tracking system, the PN chip clock is required to operate highly reliable without any glitch even under harsh environment condition such as temperature and voltage fluctu-aliens. The digital implementation of the proposed PN chip clock generator imparts it with much desired reliability. Since the proposed chip clock generator can be easily controlled into one of the states: free running, phase advance, and delay state, it can be applied to data processing as well as code synchronization. We have done FPGA implementation of the proposed logic and have verified its satisfactory operation up to 50 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.2062-2073
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• 1997

The important articles we must consider in SDH network and system design are the number of maximum nodes and clock characteristics of each node. In order to get these, the study of characteristics about some clock states, such as normal state and phase transient state, on the standard specifications is required. In this paper, we presented MTIE and TDEV characteristics with ITU-T & ANSI standard specifications in some clock states of the SDH linear networks, and proposed the number of maximum nodes satisfying above two standards. Also our resulsts are compared with AT&T's.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.181-187
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• 2003

This paper presents an 125MHz, 128-phase phase-locked loop using interpolation technique for digital timing recovery. To reduce the power consumption and chip area, phase interpolation was performed over only selected windows, instead of overall period. Four clocks were used for phase interpolation to avoid the output jitter increase due to the interpolation clock (clock used for phase interpolation) switching. Also, the output clock was fed back to finite-state machine (FSM) where the multiplexer selection signals are generated to eliminate the possible output glitches. The PLL implemented in a $0.25\mu\textrm{m}$ CMOS process and dissipates 80mW at 2.5V supply and occupies $0.84\textrm{mm}^2.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.395-400
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• 2006

Among the various error sources in positioning and navigation, the paper focuses on the modeling and prediction of receiver clock bias and then tries to achieve positioning based on simulated and predicted clock bias. With the SA off, it is possible to model receiver clock bias more accurately. We selected several types of GNSS receivers for test using ARMA model. To facilitate prediction with short and limited sample pseudorange observations, AR and ARMA are compared, and the improved AR model is presented to model and predict receiver clock bias based on previous solutions. Our work extends to clock bias prediction and positioning based on predicted clock bias using only 3 satellites that is usually the case under urban canyon situation. In contrast to previous experiences, we find that a receiver clock bias can be well modeled using adopted ARMA model. Test has been done on various types of GNSS receivers to show the validation of developed model. To further develop this work, we compare solution conditions in terms of DOP values when point positioning is conducted using 3 satellites to simulate urban positioning environment. When condition allows, height component is derived from other ways and can be set as known values. Given this condition, location is possible using less than 2 GNSS satellites with fixed height. Solution condition is also discussed for this background using mode of constrained positioning. We finally suggest an effective predictive time span based on our test exploration under varied conditions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.50-57
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• 2008

In this paper, a high-efficiency charge pump for use in CMOS image sensor(CIS) is proposed. The proposed charge pump pursues high pumping efficiency by minimizing the switching and reversion losses by taking advantage of operation characteristics of CIS. That is, the proposed charge pump minimizes the switching loss by dynamically controlling the size of clock driver, pumping capacitor, and charge transfer switch based on the operation phase of CIS pixel sensor. The charge pump also minimizes the reversion loss by guaranteeing a sufficient non-overlapping period of local clocks using a tri-state local clock driver adapting the schmitt trigger. Comparison results using a 0.13-um CMOS process technology indicate that the proposed charge pump achieves up to 49.1% reduction on power consumption under no loading current condition as compared to conventional charge pump. They also indicate that the charge pump provides 19.0% reduction on power consumption under the maximum loading current condition.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.5
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• pp.1104-1109
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• 2015

Due to the rapid growth in digital contents, it is important for us to design a high speed and secure encryption algorithm which is able to comply with the existing and future needs. This paper proposes an alternative approach for self-decimated LM-128 summation sequence generator, which will generate a higher throughput if compared to the conventional generator. We design and implement a threshold clock-controlled LM-128 and prove that it has a lower clock cycle and hence giving a higher key stream generation speed. The proposed threshold clock-control LM-128 generator consists of 256 bits inner state with 128 bits secret key and initialization vector. The cipher achieves a security level of 128 bits to be adapted to the digital contents security with high definition and high quality.