• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.140-148
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• 1993

High Integration ratio of CMOS circuits incredily increases the test cost during the design and fabrication processes because of the FET fault(Stuck-on faults and Stuck-off faults) which are due to the operational characteristics of CMOS circuits. This paper proposes a test generation algorithm for an arbitrarily large CMOS circuit, which can unify the test steps during the design and fabrication procedure and be applied to both static and dynaic circuits. This algorithm uses the logic equations set for the subroutines resulted from arbitrarily dividing the full circuit hierarchically or horizontally. Also it involves a driving procedure from output stage to input stage, in which to drive a test set corresponding to a subcircuit, only the subcircuits connected to that to be driven are used as the driving resource. With this algorithm the test cost for the large circuit such as VLSI can be reduced very much.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.12
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• pp.8-14
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• 2015

An effective way to ensure that LEDs produce wanted light output is to use a current driving topology, because the brightness of LEDs is directly related to their current. However, this topology may lead to the lifetime shortening of a illumination system because over-currents may flow through non-damaged LEDs in case some LEDs are damaged. This paper presents an adaptive current control circuits for LEDs, which protect LEDs in a good state by limiting the driving currents according to the number of damaged ones. The proposed control circuits consist of a simple constant-current driver and a micro-controller which monitors the voltage of LED array without any auxiliary current sensors for fault diagnosis. And the driving current is automatically controlled into 6-levels according to the number of failures.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.359-362
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• 2010

In this study, inverter logic circuits on a plastic substrate are built with two top-gate FETs in series on a single ZnO nanowire. The voltage transfer characteristics of the ZnO nanowire-based inverter logic circuit exhibit a clear inverting operation. The logic swing, gain and transition width of the inverter logic circuit is about 90 %, 1.03 and 1.2 V, respectively. The result of mechanical bending cycles of the inverter logic circuit on a plastic substrate shows that the stable performance is maintained even after many hundreds of bending cycles.

• Journal of Electrical Engineering and Technology
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• v.7 no.3
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• pp.297-303
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• 2012

This paper presents the simulation results for the analysis of a lightning surge, switching transients and very fast transients within a thermal plant. The modeling of gas insulated substations (GIS) makes use of electrical equivalent circuits that are composed of lumped elements and distributed parameter lines. The system model also includes some generators, transformers, and low voltage circuits such as 24V DC rectifiers and control circuits. This paper shows the simulation results, via EMTP (Electro-Magnetic Transients Program), for three overvoltage types, such as transient overvoltages, switching transients, very fast transients and a lightning surge.

• Journal of Power Electronics
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• v.9 no.4
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• pp.567-574
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• 2009

A linear transfer function for the output current control of frequency-controlled resonant inverters is proposed in this paper. The circuit of resonant inverters can be transformed into two coupled circuits through the complex phasor transform. The circuits consist of cross-coupled power sources and passive elements. The circuits are used to induce the state space equation, which is transformed into the $4^{th}$ order cross-coupled transfer function. The $4^{th}$ order cross-coupled transfer function is modeled into a $2^{nd}$ order linear transfer function based on a behavior analysis of the pole and zero locations that facilitate a simple and intuitive linear transfer function. The feasibility and validity of the proposed linear transfer function were verified by simulation and experiment.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.67-70
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• 2009

Printed electronics are emerging technology to realize various microelectronic devices via a cost-effective method. Here we introduce high performance inkjet printed polymer field-effect transistors and application to complementary integrated circuits with p-type and n-type conjugated polymers. The performance of devices highly depends on the selection of dielectrics, printing condition and device architecture. The device optimization and performances of various integrated circuits, e.g., complementary inverters and ring oscillators will be mainly discussed in this talk.

• Journal of Information Processing Systems
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• v.7 no.1
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• pp.93-102
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• 2011

In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel post-silicon tuning methodology to scale optimum voltage and frequency "dynamically". The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated "automatically". During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS'85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method.

• ETRI Journal
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• v.30 no.4
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• pp.546-554
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• 2008

Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.

• ETRI Journal
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• v.33 no.5
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• pp.818-821
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• 2011

A D-band subharmonically-pumped resistive mixer has been designed, processed, and experimentally tested. The circuit is based on a $180^{\circ}$ power divider structure consisting of a Lange coupler followed by a ${\lambda}$/4 transmission line (at local oscillator (LO) frequency). This monolithic microwave integrated circuit (MMIC) has been realized in coplanar waveguide technology by using an InAlAs/InGaAs-based metamorphic high electron mobility transistor process with 100-nm gate length. The MMIC achieves a measured conversion loss between 12.5 dB and 16 dB in the radio frequency bandwidth from 120 GHz to 150 GHz with 4-dBm LO drive and an intermediate frequency of 100 MHz. The input 1-dB compression point and IIP3 were simulated to be 2 dBm and 13 dBm, respectively.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1005-1008
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• 2000

This paper presents a simple method to estimate short-circuit power dissipation and propagation delay for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. The macro model and its expressions estimating the delay of CMOS circuits, which is based on the current modeling expression, are also proposed after investigating the voltage waveforms at transistor output modes. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.