• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.992-996
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• 2004

Small electric motors in an automobile perform various tasks such as engine cooling, pumping, and in heating, ventilating, and air-conditioning (HVAC) system. At present, most of dc motors are supplied by 12V or 24V batteries. However, DC motors surfer from lack of efficiency, low life cycles and unreliability. Therefore, there is a growing interest in substituting DC motors for advanced AC motors including switched reluctance motors. Although there are several other forms SRM converters, they are either unsatisfactory to the control performance or unsuitable for the 12V-battery powered 3-phase SRM drives. Taking into account the requirement for effective operation and simplicity structure of converter in the limited internal environment of automobiles, the author inclines toward selecting the modified C-dump converter as well as the energy efficient C-dump converter. This is so that more economical and efficient converter topology in automobile industries can be utilized. This paper describes the foundation for the design and development of a 12V-250W-3000rpm SRM drives for automobiles. Furthermore, complete circuit, computer simulation and experiment results are presented to verify the performance of the C-dump converters.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.2
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• pp.35-41
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• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.5
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• pp.939-944
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• 2010

A high voltage air-cored helical strip/wire type pulse transformer has been fabricated for charging of a high voltage pulse forming line. As a primary coil, copper strip of 25mm width was wound helically around a MC nylon cylinder. For a secondary coil, copper enameled wire of 1mm diameter was wound around conical cylinder in order to provide insulation between two windings. The coupling coefficient of 0.53 was obtained when two coils were combined coaxially in the insulation oil filled chamber. Voltage gain and energy transfer efficiency were investigated by varying the parameters of primary and secondary circuit. Test results shows that the voltage gain increases up to 17 with increasing the primary capacitance up to 200nF. And highest energy transfer efficiency of 44% was obtained when the dual resonant operation condition was nearly satisfied. The pulse transformer developed in this study can be used for charging the middle conductor of a Blumlein pulse forming line.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.2
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• pp.71-76
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• 2016

A controller area network (CAN) receiver measures differential voltage on a bus to determine the bus level. Since 3.3V transceivers generate the same differential voltage as 5V transceivers (usually ${\geq}1.5V$), all transceivers on the bus (regardless of supply voltage) can decipher the message. In fact, the other transceivers cannot even determine or show that there is anything different about the differential voltage levels. A new CMOS RC oscillator insensitive supply voltage for clock generation in a CAN transceiver was fabricated and tested to compensate for this drawback in CAN communication. The system consists of a symmetrical circuit for voltage and current switches, two capacitors, two comparators, and an RS flip-flop. The operational principle is similar to a bistable multivibrator but the oscillation frequency can also be controlled via a bias current and reference voltage. The chip test experimental results show that oscillation frequency and power dissipation are 500 kHz and 5.48 mW, respectively at a supply voltage of 3.3 V. The chip, chip area is $0.021mm^2$, is fabricated with $0.18{\mu}m$ CMOS technology from SK hynix.

• ETRI Journal
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• v.20 no.1
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• pp.55-73
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• 1998

In this paper we analyze the technological accumulation processes in the Korean semiconductor industry from the institutional approach. Institutional approach, which is closely connected with Neo-Schumpeterian tradition, has emerged as an alternative theoretical framework to neoclassical approach to understand the process of producing technological knowledge. Traditional wisdom of neoclassical approach revealed the limitation to explain the complex nature of knowledge creation and diffusion. US patent data are analyzed in terms of the increasing trend of numbers and its content to measure the rate and direction of technological capability accumulation. This analysis shows that semiconductor technologies are one of the fastest growing fields among Korean technological activities. Moreover, the analysis of patent content suggests that fabrication technologies are the most important area within the technological development of semiconductors, whilst circuit design and testing technologies are beginning to increase in significance. In addition, it is examined how private sectors and public institutions have contributed to generate technological capabilities, and the relationship between them has been changed during the development processes. It is found that Korean firms enhanced their technological capabilities from the learning and assimilation of imported technology to enhanced in-house R&D capabilities in the later stage. The support of public institution and government policy also played significant role to this successful transformation in conjunction with vigorous R&D investment of public sector.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1022-1032
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• 2002

A multibit DRAM BIST methodology reducing redundancy programming overhead has been proposed. It is capable of counting and locating faulty bits simultaneously with the test. If DRAM cells are composed of n blocks generally, the proposed BIST can detect the state of no error, the location of faulty bit block if there is one error and the existence of errors in more than two blocks, which are n + 2 states totally, with only n comparators and an 3 state encoder. Based on the proposed BIST methodology, the testing scheme which can detect the number and locations of faulty bits with the errors in two or more blocks, can be easily implemented. Based on performance evaluation, the test and redundancy programming time of 64MEG DRAM with 8 blocks is reduced by 1/750 times with 0.115% circuit overhead.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1894-1903
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• 2016

In general, electrolytic capacitors are used to reduce power pulsations on PV-panels. However, this can reduce the reliability of the PV AC-module system, because electrolytic capacitors have a shorter lifetime than PV-panels. In addition, PV-panels generate irregular power and inject it into the grid because the output power of a PV-panel depends on the surrounding conditions such as irradiation and temperature. To solve these problems, a grid-connected photovoltaic (PV) AC-module with active power decoupling and energy storage is proposed. A parallel bi-directional converter is connected to the AC module to reduce the output power pulsations of PV-panels. Thus, the electrolytic capacitor can be replaced with a film capacitor. In addition, the irregular output power due to the surrounding conditions can be regulated by using a parallel energy storage circuit. To maintain the discontinuous conduction mode at low irradiation, the frequency control method is adopted. The design method of the proposed converter and the operation principles are introduced. An experimental prototype rated at 125W was built to verify the performance of the proposed converter.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.1
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• pp.99-107
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• 2001

In this paper, we implemented memory BIST circuit based on ION march algorithm, and the IEEE 1149.1 has been designed as main controlJer for embedded memory testing. The implemented memory BIST can be used for word-oriented memory since it adopts background data, this is avaliable for word-oriented memory. It is able to detect all stuck-at faults, transition faults, coupling faults, and address decoder faults in the word-oriented memory. Memory BIST and IEEE 1149.1 are described at RTL level in Verilog-HDL, and synthesized with the Synopsys. The synthesized circuits are fully velified using VerilogXL and memory cell generated by memory compiler.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.7
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• pp.359-364
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• 2000

This paper is introducing a newly developed spark-gap switch with dual trigger system, into which the current from the voltage source is injected along with the test sequence during the synthetic testing of high voltage circuit-breaker. The currently-used spark gap switch is narrow in operating range due to the use of the method of triggering energy being injected by single way. As a result, the frequent happening of misoperation has greatly reduced the test quality and test efficiency and has required the cost of maintenance excessively. In this study, accordingly, in order to basically remove these problems, another triggering system is installed to the opposite direction on the existing triggering system; attaching the same time and the same rising time of pulse wave as on the existing system, so that at a comparatively trigger gap distance from the main electrode(the gap can be operated at 60% of self-break voltage, while at 80% in the current system), the main electrode has been enabled to be closed by the development of spark gap switch with dual trigger system.

• Proceedings of the KIEE Conference
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• 2002.04a
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• pp.96-98
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• 2002

This paper proposes the digital pin line checker which can extremely improve the efficiency of the pine line checking using a micro processor. The line checker is designed which can check efficiently up to maximum 2048 pin. Alarm busser is designed ringing real-timely the case that the pin line is connected differently with real node number. Accordingly the comparing and identifying work visually the node number showing on the displaying board with real node number is avoided after the electronic stimulus enforce to the pin of the fixture by the test engineer. The digital line checker is designed based on the 8051. And the effectiveness and accuracy of the proposed line checking strategy is tested by simulating the several error connections for pin lines on the small scale board.