• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.114-126
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• 2013

In this paper, we present a set of methodologies to model the electromagnetic susceptibility (EMS) testing of I/O buffers for mobile system memory based on the bulk current injection (BCI) method. An efficient equivalent circuit model is developed for the current injection probe, line impedance stabilization network (LISN), printed circuit board (PCB), and package. The simulation results show good correlation with the measurements and thus, the work presented here will enable electromagnetic susceptibility analysis at the integrated circuit (IC) design stage.

• 한국전자통신학회논문지
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• 제11권2호
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• pp.179-184
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• 2016

본 연구를 통해 개발된 전기부하시험장치는 상용전원이 필요한 피시험장치(변압기, 정류기, 전압조정기, 인버터 등)와 상용전원이 불필요한 독립형 피시험장치(동력발전기, 풍력발전장치, 태양광발전장치, 하이브리드발전 장치, 배터리 등)에 대하여 정격용량시험이나 가변부하시험을 능동적으로 정밀하게 제어하면서도 시험 중에 사용되는 전기에너지를 소비하지 않고 전원변환장치를 통하여 계통선으로 전달하도록 설계되었다. 동기식 pwm 인버터회로를 상용전원과 연결시켜서 시험에 사용되는 전력을 계통선으로 귀환되도록 설계되었으며, 종전의 수동식 전기저항체를 사용한 전기부하시험장치에 비해 93.4% 정도의 전력을 소모하지 않고도 피시험체에 대한 시험이 가능하도록 하였다.

• ETRI Journal
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• 제25권3호
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• pp.187-194
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• 2003

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45 % over the conventional functional justification.

• Journal of Electrical Engineering and Technology
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• 제2권4호
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• pp.441-444
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• 2007

The mechanical endurance is the critical characteristic of Magnetic contactors (MCs), which are widely used in such industrial equipments as elevators, cranes, and factory control rooms in order to close and open the control circuit. Testing time, however, is so long in most cases that some method of reducing the testing period is required. Therefore, the degradation test by the detected vibration of MCs is developed to reduce the testing time in this work. The degradation test data are analyzed and the prediction model is provided. Also, the possibility of this technology for Reliability Centered Maintenance (RCM) will be shown. This will reduce the period of the product development and raise the reliability of the equipment in power distribution.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 B
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• pp.757-759
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• 2001

전동기 전원 개폐를 주목적으로 하는 전자개폐기는 빈번하고 불규칙한 개폐동작에 의해 발생되는 Arc 에너지에 대해 전기적으로 내구성능을 확보하는 것이 중요하다. 또한, 전기적 내구 성능은 수명과 품질을 결정하는 요인으로서 선진업체에서는 내구성능을 향상시키려 연구개발 활동에 집중하고 있다. 이러한 전기적 내구 성능을 향상, 평가하기 위해서는 장기간에 걸친 시험 기간과 시험규격에서 요구하는 조건을 만족시키는 시험 회로와 설비구성이 필수적이다. 여기서는 전기적 내구 성능에 대한 이해와 시험규격을 통한 시험회로 설계 및 설비제작에 대해 설명하고 시험결과를 분석하고자 한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.151-153
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• 2002

전자화 기기의 신뢰성이 요구되는 산업환경에서 외부잡음, 방사잡음, 전도 노이즈 등으로 인한 제품의 오동작 및 기능장해 문제가 발생되고 있다. 저압용 배선용 차단기 또한 네트워크를 통한 통신, 감시(monitoring). 제어(control) 둥의 기능을 구현하기 위한 전자회로를 탑재한 전자식 제품의 개발이 활발이 이루어지고 있으며 정화한 시험을 통한 검증이 필요하다. 본 논문에서는 전자회로 트림장치를 가진 전자식 차단기에 대한 IEC947-2에서 요구하는 EMC 시험방법을 고찰하고자 한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.271-274
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• 2003

This paper presents a Built-in Current Sensor that detect defects in CMOS integrated circuits using the current testing technique. This scheme employs a cross-coupled connected PMOS transistors, it is used as a current comparator. Our proposed scheme is a negligible impart on the performance of the circuit undo. test (CUT). In addition, in the normal mode of the CUT not dissipation extra power, high speed detection time and applicable deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The entire area of the test chip is $116{\times}65{\mu}m^2$. The BICS occupies only $41{\times}17{\mu}m^2$ of area in the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS technology.

• Journal of Electrical Engineering and Technology
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• 제8권4호
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• pp.787-798
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• 2013

This paper proposes a special power circuit topology and its corresponding control strategy for an energy recovery power accumulator battery pack testing system (PABPTS), which is particularly used in electric vehicles. Firstly, operation principle and related parameter design for the system are illustrated. Secondly, control strategy of the composite power converter for PABPTS is analyzed in detail. The improved scheme includes a high accuracy charge and discharge current closed loop. active power reference for the grid-side inverter is provided by the result of multiplication between battery pack terminal voltage and test current. Simulation and experimental results demonstrate that the proposed scheme could not only satisfy the requirements for PABPTS with wide-range current test, but also could recover the discharging energy to the power grid with high efficiency.

• Journal of Power Electronics
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• 제16권2호
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• pp.786-797
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• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

• 전력전자학회논문지
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• 제17권3호
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• pp.191-197
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• 2012

This paper proposes a new synthetic test circuit (STC) to confirm the switching operation of thyristor valve in HVDC converter. The proposed STC uses a 6-pulse thyristor converter with 2-phase chopper as a high-current source to provide turn-on current to the test valve. The operation of proposed STC was verified through theoretical analysis and computer simulations. Based on computer simulations, a hardware scaled model was built and tested to confirm the feasibility of implementing a real-size test facility. The proposed system has an advantage of simple structure and operation over the existing system.