• Title/Summary/Keyword: Circuit Parameter

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A study on the dynamic characteristics of the secondary loop in nuclear power plant

  • Zhang, J.;Yin, S.S.;Chen, L.;Ma, Y.C.;Wang, M.J.;Fu, H.;Wu, Y.W.;Tian, W.X.;Qiu, S.Z.;Su, G.H.
    • Nuclear Engineering and Technology
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    • v.53 no.5
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    • pp.1436-1445
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    • 2021
  • To obtain the dynamic characteristics of reactor secondary circuit under transient conditions, the system analysis program was developed in this study, where dynamic models of secondary circuit were established. The heat transfer process and the mechanical energy transfer process are modularized. Models of main equipment were built, including main turbine, condenser, steam pipe and feedwater system. The established models were verified by design value. The simulation of the secondary circuit system was conducted based on the verified models. The system response and characteristics were investigated based on the parameter transients under emergency shutdown and overload. Various operating conditions like turbine emergency shutdown and overspeed, condenser high water level, ejector failures were studied. The secondary circuit system ensures sufficient design margin to withstand the pressure and flow fluctuations. The adjustment of exhaust valve group could maintain the system pressure within a safe range, at the expense of steam quality. The condenser could rapidly take out most heat to avoid overpressure.

RC Circuit Parameter Estimation for DC Electric Traction Substation Using Linear Artificial Neural Network Scheme (선형인공신경망을 이용한 직류 전철변전소의 RC 회로정수 추정)

  • Bae, Chang Han;Kim, Young Guk;Park, Chan Kyoung;Kim, Yong Ki;Han, Moon Seob
    • Journal of the Korean Society for Railway
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    • v.19 no.3
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    • pp.314-323
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    • 2016
  • Overhead line voltage of DC railway traction substations has rising or falling characteristics depending on the acceleration and regenerative braking of the subway train loads. The suppression of this irregular fluctuation of the line voltage gives rise to improved energy efficiency of both the railway substation and the trains. This paper presents parameter estimation schemes using the RC circuit model for an overhead line voltage at a 1500V DC electric railway traction substation. A linear artificial neural network with a back-propagation learning algorithm was trained using the measurement data for an overhead line voltage and four feeder currents. The least square estimation method was configured to implement batch processing of these measurement data. These estimation results have been presented and performance analysis has been achieved through raw data simulation.

A Coaxial Band Rejection Filter using a Quarter Wavelength Choke Structure (4분의 1 파장 초크 구조를 이용한 동축형 대역억제필터)

  • Han, Dae Hyun
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.11 no.3
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    • pp.313-318
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    • 2018
  • A coaxial band rejection filter is designed and fabricated for a beam interacting cavity. The proposed filter has a quarter wavelength choke for the dominant mode of the cavity. The equivalent circuit of the coaxial band rejection filter is presented and the ABCD parameter os each part is derived to obtain the ABCD parameter of the entire filter. The scattering matrix was obtained from the ABCD matrix and the was simulated by MATLAB using the obtained scattering matrix. The coaxial band rejection filter structure was simulated using HFSS, and the results confirmed the simulation using the equivalent circuit was useful. The designed coaxial band rejection filter was fabricated with 6-1/8 flange. The fabricated filter was measured using a transition from 6-1/8 flange to N-type flange. The insertion loss of the fabricated filter is greater than 25 dB in the dominant mode of the cavity and less than 0.25 dB in the first higher order mode. The measurement results are in good agreement with the simulated results and meet the design specification.

Computation of the Critical Lengths of the Vertical Grounding Electrode in Multi-Layered Soil Structures (다층 대지구조에서 수직 접지전극의 임계길이 산정)

  • Kim, Ki-Bok;Joe, Jeong-Hyeon;Lee, Bok-Hee
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.24 no.4
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    • pp.73-80
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    • 2010
  • The grounding impedance is not lowered by expanding the dimension of the grounding electrode, and the length of grounding electrode which shows the minimum value of the grounding impedance for each condition of frequency and soil characteristics is existent, and it is defined as Critical Length. In this paper, a new distributed parameter circuit model considering the condition of the multi-layered soil structures was proposed, and the grounding impedance and critical length of the vertical grounding electrode were analyzed by using the newly proposed simulation model and the MATLAB program. As a consequence, it was found that the effect of the soil structure on the frequency-dependent grounding impedance and critical length of the vertical grounding electrode is significant. It is desirable to consider the soil structure in optimal design of the grounding system.

Design of a MOSFET Monostable Multivibrator by Graphical Method (도식방법에 의한 MOSFET 단안정 멀티바이브레이터의 설계)

  • 심수보
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.13 no.1
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    • pp.11-15
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    • 1976
  • In a MOSFET multivibrator, the gate do not hold into a constant clamp voltage during a conduction period. The analysis of the operation and the 43sign of a MOSFET multivibrator circuit are much more discult than that using a bipolar transistor and a electron tube because of above reason. And therefore, in the designing procedures of the MOSFET monostable multivibrator of this paper, a graphical method is adopted in order to analyze and design easily. The voltage gain curves of the both FETs are drawn using a parameter the voltage Vc across the coupling condenser, and the curves are utilized to investigate the voltages of the drains and the gates and determine the gate bias voltage. The diagram gives also important informations for the design of the multivibrator.

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A New Parallelizing Algorithm and Cell-based Hardware Architecture for High-speed Generation of Digital Hologram (디지털 홀로그램의 고속 생성을 위한 병렬화 알고리즘 및 셀 기반의 하드웨어 구조)

  • Seo, Young-Ho;Choi, Hyun-Jun;Yoo, Ji-Sang;Kim, Dong-Wook
    • Journal of Broadcast Engineering
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    • v.16 no.1
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    • pp.54-63
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    • 2011
  • This paper proposes a new equation to calculate computer-generated hologram (CGH) in a high speed and its cell-based VLSI (veri large scale integrated circuit) architecture. After finding the calculational regularity in the horizontal or vertical direction from the basic CGH equation, we induce the new equation to calculate the horizontal or vertical hologram pixel values in parallel. We also propose the architecture of the CGH cell consisting of a initial parameter calculator and update-phase calculator(s) on the basis of the equation and implement them in hardware. Also we show a hardware architecture to parallelize the calculation in the horizontal direction by extending CGH. In the experiments we analyze the used hardware resources. These analyses makes it possible to select the amount of hardware to the precision of the results. Here, for the CGH kernel and the structure of the processor, we used the platform from our previous works.

Reduced-order Mapping and Design-oriented Instability for Constant On-time Current-mode Controlled Buck Converters with a PI Compensator

  • Zhang, Xi;Xu, Jianping;Wu, Jiahui;Bao, Bocheng;Zhou, Guohua;Zhang, Kaitun
    • Journal of Power Electronics
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    • v.17 no.5
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    • pp.1298-1307
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    • 2017
  • The constant on-time current-mode controlled (COT-CMC) switching dc-dc converter is stable, with no subharmonic oscillation in its current loop when a voltage ripple in its outer voltage loop is ignored. However, when its output capacitance is small or its feedback gain is high, subharmonic oscillation may occur in a COT-CMC buck converter with a proportional-integral (PI) compensator. To investigate the subharmonic instability of COT-CMC buck converters with a PI compensator, an accurate reduced-order asynchronous-switching map model of a COT-CMC buck converter with a PI compensator is established. Based on this, the instability behaviors caused by output capacitance and feedback gain are investigated. Furthermore, an approximate instability condition is obtained and design-oriented stability boundaries in different circuit parameter spaces are yielded. The analysis results show that the instability of COT-CMC buck converters with a PI compensator is mainly affected by the output capacitance, output capacitor equivalent series resistance (ESR), feedback gain, current-sensing gain and constant on-time. The study results of this paper are helpful for the circuit parameter design of COT-CMC switching dc-dc converters. Experimental results are provided to verify the analysis results.

Dynamic-Response-Free SMPS Using a New High-Resolution DPWM Generator Based on Switched-Capacitor Delay Technique (Switched-Capacitor 지연 기법의 새로운 고해상도 DPWM 발생기를 이용한 Dynamic-Response-Free SMPS)

  • Lim, Ji-Hoon;Park, Young-Kyun;Wee, Jae-Kyung;Song, In-Chae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.1
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    • pp.15-24
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    • 2012
  • In this paper, we suggest the dynamic-response-free SMPS using a new high-resolution DPWM generator based on switched-capacitor delay technique. In the proposed system, duty ratio of DPWM is controlled by voltage slope of an internal capacitor using switched-capacitor delay technique. In the proposed circuit, it is possible to track output voltage by controlling current of the internal capacitor of the DPWM generator through comparison between the feedback voltage and the reference voltage. Therefore the proposed circuit is not restricted by the dynamic-response characteristic which is a problem in the existing SMPS using the closed-loop control method. In addition, it has great advantage that ringing phenomenon due to overshoot/undershoot does not appear on output voltage. The proposed circuit can operate at switching frequencies of 1MHz~10MHz using internal operating frequency of 100 MHz. The maximum current of the core circuit is 2.7 mA and the total current of the entire circuit including output buffer is 15 mA at the switching frequency of 10 MHz. The proposed circuit has DPWM duty ratio resolution of 0.125 %. It can accommodate load current up to 1 A. The maximum ripple of output voltage is 8 mV. To verify operation of the proposed circuit, we carried out simulation with Dongbu Hitek BCD $0.35{\mu}m$ technology parameter.

Radio Frequency Circuit Module BGA(Ball Grid Array) (Radio Frequency 회로 모듈 BGA(Ball Grid Array) 패키지)

  • Kim, Dong-Young;Jung, Tae-Ho;Choi, Soon-Shin;Jee, Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.1
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    • pp.8-18
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    • 2000
  • We presented a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. As the frequency of RF system devices increases, the effect of its electrical parasitics in the wireless communication system requires new structure of RF circuit modules because of its needs to be considered of electrical performance for minimization and module mobility. RF circuit modules with BGA packages can provide some advantages such as minimization, shorter circuit routing, and noise improvement by reducing electrical noise affected to analog and digital mixed circuits, etc. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and measured electrical parameters with a TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3${\times}$3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, and self inductance 146pH, whose values were reduced to 34% and 47% of the value of QFP package structure. S11 parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55GHz and the loss of 0.26dB. Routing length of the substrate was reduced to 39.8mm. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

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Electrical Behavior of the Circuit Screen-printed on Polyimide Substrate with Infrared Radiation Sintering Energy Source (열소결로 제작된 유연기판 인쇄회로의 전기적 거동)

  • Kim, Sang-Woo;Gam, Dong-Gun;Jung, Seung-Boo
    • Journal of the Microelectronics and Packaging Society
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    • v.24 no.3
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    • pp.71-76
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    • 2017
  • The electrical behavior and flexibility of the screen printed Ag circuits were investigated with infrared radiation sintering times and sintering temperatures. Electrical resistivity and radio frequency characteristics were evaluated by using the 4 point probe measurement and the network analyzer by using cascade's probe system, respectively. Electrical resistivity and radio frequency characteristics means that the direct current resistance and signal transmission properties of the printed Ag circuit. Flexibility of the screen printed Ag circuit was evaluated by measuring of electrical behavior during IPC sliding test. Failure mode of the Ag printed circuits was observed by using field emission scanning electron microscope and optical microscope. Electrical resistivity of the Ag circuits screen printed on Pl substrate was rapidly decreased with increasing sintering temperature and durations. The lowest electrical resistivity of Ag printed circuit was up to $3.8{\mu}{\Omega}{\cdot}cm$ at $250^{\circ}C$ for 45 min. The crack length arisen within the printed Ag circuit after $10{\times}10^4$ sliding numbers was 10 times longer than that of after $2.5{\times}10^4$ sliding numbers. Measured insertion loss and calculated insertion loss were in good agreements each other. Insertion loss of the printed Ag circuit was increased with increasing the number of sliding cycle.