• KIPS Transactions on Computer and Communication Systems
• /
• v.4 no.12
• /
• pp.391-398
• /
• 2015

This paper devises a performance improvement and evaluation process of circuit minimization algorithms for mentorship education of distinguished informatics gifted secondary students. In the process, students learn that there are several alternative equivalent circuits for a target function and recognize the necessity for formalized circuit minimization methods. Firstly, they come at the concept of circuit minimization principle from Karnaugh Map which is a manual methodology. Secondly, they explore Quine-McCluskey algorithm which is a computational methodology. Quine-McCluskey algorithm's time complexity is high because it uses set operations. To improve the performance of Quine-McCluskey algorithm, we encourage them to adopt a bit-wise data structure instead of integer array for sets. They will eventually see that the performance achievement is about 36%. The ultimate goal of the process is to enlarge gifted students' interest and integrated knowledge about computer science encompassing electronic switches, logic gates, logic circuits, programming languages, data structures and algorithms.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.13 no.4
• /
• pp.12-17
• /
• 1976

This paper deals with characteristics and analysis of the Universal Logic Modules as well as TULM, QULM and SULM. Studies are made on minimization in Storms of symmetric circuits and theoretical stuides are made by using the symmetric functions The symmetric circuits of the ULM are realized by employing 54/74 ICs, An oscillator circuit of 10KHz. is constructed based on the ULM. The experimental results gave a good agreement with the theoretical Minimization.

• Journal of the Korea Society of Computer and Information
• /
• v.19 no.3
• /
• pp.109-117
• /
• 2014

This paper revises the Quine-McCluskey Algorithm to circuit minimization problems. Quine-McCluskey method repeatedly finds the prime implicant and employs additional procedures such as trial-and-error, branch-and-bound, and Petrick's method as a means of circuit minimization. The proposed algorithm, on the contrary, produces an implicant chart beforehand to simplify the search for the prime implicant. In addition, it determines a set cover to streamline the search for $1^{st}$ and $2^{nd}$ essential prime implicants. When applied to 3-variable and 4-variable experimental data, the proposed algorithm has indeed proved to obtain the optimal solutions much more simply and accurately than the Quine-McCluskey method.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.8
• /
• pp.84-91
• /
• 2002

In this paper, we proposed a CLB-based CPLD technology mapping algorithm for power minimization under time constraint in combinational circuit. The main idea of our algorithm is to exploit the "cut enumeration and feasible cluster" technique to generate possible mapping solutions for the sub-circuit rooted at each node. In our technology mapping algorithm conducted a low power by calculating TD and EP of each node and decomposing them on the circuit composed of DAG. It also takes the number of input, output, and OR-term into account on condition that mapping can be done up to the base of CLB, and so it generates the feasible clusters to meet the condition of time constraint. Of the feasible clusters, we should first be mapping the one that h3s the least output for technology mapping of power minimization and choose to map the other to meet the condition of time constraint afterwards. To demonstrate the efficiency of our approach, we applied our algorithm to MCNC benchmarks and compared the results with those of the exiting algorithms. The experimental results show that our approach is shown a decrease of 46.79% compared with DDMAP and that of 24.38% for TEMPLA in the power consumption.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.388-391
• /
• 1999

This Paper presents an efficient algorithm that minimizes the area of the combinational system through cell replacement. During the minimization, it maintains the circuit speed same. For the minimization, the proposed algorithm defines the criticality of each cell, based on the critical delay and the number of paths passing through the cell. Then, it visits the cells of the system, one by one, from the one with the lowest criticality, and replaces it with the minimum area cell that satisfies the delay constraint. Experimental results, using the LGsynth91 benchmark circuits synthesized by misII, show that the proposed algorithm reduces the circuit area further by 17.54% on the average without sacrificing the circuit speed.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.60 no.6
• /
• pp.1140-1145
• /
• 2011

This paper proposes a new loss minimization control method for the vector controlled induction motors. The aim of the proposed loss minimization method is how to determine the optimal flux reference to minimize the total loss of induction motor. Even though the proposed algorithm is based on the equivalent circuit of induction motor including iron loss and leakage inductance, the algorithm is easy to be found and simple to be implemented. Futhermore, the proposed loss minimization algorithm can be applied easily to the traditional vector control system without any additional hardware. Simulation and experimental results are given to validate the effectiveness of the proposed method.

• Journal of KIISE:Computer Systems and Theory
• /
• v.30 no.9
• /
• pp.504-511
• /
• 2003

The property of circuit symmetry has long been applied to the Problem of minimizing the area and timing of multi-level logic circuits. In this paper, we focus on another important design objective, power minimization, utilizing circuit symmetries. First, we analyze and establish the relationship between several types of circuit symmetry and their applicability to reducing power consumption of the circuit, proposing a set of re-synthesis techniques utilizing the symmetries. We derive an algorithm for detecting the symmetries (among the internal signals as well as the primary inputs) on a given circuit implementation. We then propose effective transformation algorithms to minimize power consumption using the symmetry information detected from the circuit. Unlike many other approaches, our transformation algorithm guarantees monotonic improvement in terms of switching activities, which is practically useful in that user can check the intermediate re-synthesized designs in terms of the degree of changes of power, area, timing, and the circuit structure. We have carried out experiments on MCNC benchmark circuits to demonstrate the effectiveness of our algorithm. On average we reduced the power consumption of circuits by 12% with relatively little increase of area and timing.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.22 no.2
• /
• pp.82-89
• /
• 1985

A new non-inferior solution is obtained by investigating method of weight p- norm to explain the conception of MCO (multiple criterion optimization) problem. And then the optimum non-inferior solution is obtained by the weight minimization method applied to objective function of MOSFET NAND rATEAlso this weight minimization method using weight P- norm methods can be applied to non-convex objective function. The result of this minimization method shows the efficiency in comparison with that of Lightner.

• Proceedings of the KIPE Conference
• /
• 2009.11a
• /
• pp.252-255
• /
• 2009

This paper proposes a new loss minimization controller (LMC) for induction motor drive. The proposed LMC presents a strategy to minimize the total power losses of induction motor (IM), which is based on simplified equivalent circuit and simplified model of IM. The proposed controller using the field oriented control (FOC) method is to determine an optimal rotor flux for obtaining the minimum total power losses and higher efficiency. Simulation and experimental results are given to validate the effectiveness of the proposed method.

• Proceedings of the KIEE Conference
• /
• 1995.07b
• /
• pp.623-627
• /
• 1995

This paper describes analysis and optimization of Weil-Dobke synthetic testing circuit parameters, which is efficient and economical test method in high capacity AC circuit breaker. In this paper, analysis of synthetic short-circuit test circuit parameter proposed nondimensional factor that is reciprocal comparison value of circuit parameter and is not related to rated of circuit breaker, in particular, this study induce minimization of required energy of critical TRV generation specified in IEC 56 standards and present optimal design of synthetic short circuit testing facilities.