• 한국전기전자재료학회논문지
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• 제19권12호
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• pp.1099-1105
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• 2006

In this paper, the equivalent circuit model of a Rosen-type multilayer piezoelectric transformer(MPT) has been proposed based on the Mason's equivalent circuit model and the principle of single layer piezoelectric plate. From the piezoelectric direct and converse effects, the symbolic expressions between the electric inputs and outputs of the MPT have been derived from the equivalent circuit model. A simplified equivalent circuit model of the MPT whose driving part has a single input form has been proposed. The symbolic expressions of the driving part have been derived from the simplified equivalent circuit model and the model was compared with the multi-input equivalent circuit model through the simulation. In the comparisons between the simulation results and the experimental data, output voltage is 630 Vp-p in case of 11-layered MPT and 670 Vp-p for 13-layered MPT over the experiment range. As the load resistance increases, output voltage increases and saturates over $300k{\Omega}$ and the resonant frequency changes from 102 kHz to 103 kHz. The simulation and the experimental results agree well over different load resistances and frequencies.

• 전자공학회논문지C
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• 제35C권6호
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• pp.48-55
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• 1998

본 논문에서는 테스트가 용이하도록 ECC(error checking circuit)를 내장하여 테스트를 수행할 수 있는 CAM(content addressable memory)를 설계하였다. 즉, CAM에서 발생하는 읽기, 쓰기 및 매치 동작의 기능 고장을 검사할 수 있는 회로를 내장한 CAM을 설계하였다. 일반적으로 테스트 회로를 내장하면 전체면적의 증가를 가져오게 된다. 본 논문에서는 기존의 병렬 비교기를 사용한 내장(built-in) 테스트 회로의 면적 오버헤드를 줄이기 위해서 새로 제안된 MTA 코드를 이용하였다. 설계한 회로는 VHDL 시뮬레이션을 통하여 검증하였으며, 0.B㎛ double-metal CMOS 공정을 이용하여 레이아웃을 수행하였다. ECC 회로의 경우 CAM의 기본 셀에서 매치기능을 담당하고 있는 XOR회로를 이용함으로써 약 30%정도 면적 감소를 가져왔다.

• 대한기계학회논문집B
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• 제35권9호
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• pp.897-902
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• 2011

PEMFC 의 내부에서 발생하는 화학반응은 계면의 물리적 조건 및 물성에 지배되고 그 거동은 임피던스로 표현된다. 일반적으로 임피던스 특성은 전기적 등가회로로 표현이 가능하기 때문에 PEMFC의 임피던스 계측 결과를 등가회로를 이용하여 해석함으로써 간단히 성능 진단을 할 수 있을 것이다. 본 연구에서는 이러한 등가회로를 이용하여 고분자 전해질 연료전지의 특성평가에 관한 기초연구를 수행하였다. 교류 임피던스 계측 값과 다양한 등가회로(단순 등가회로, CPE 를 고려한 등가회로, 2 개의 시정수를 고려한 등가회로, 2 개의 CPE 를 고려한 등가회로)를 이용하여 특성평가를 수행하였다. 그 결과 등가회로를 이용한 PEMFC 의 특성평가가 가능하고, 2 개의 CPE 를 고려한 등가회로가 가장 정도가 높음을 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 추계학술대회 논문집 전력기술부문
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• pp.340-343
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• 2001

In an electrical network, electrical power are transmitted by a various of protection, isolation and control electric circuit devices. This thesis deals with the protection function between circuit-breakers. The protective coordination concerns the behaviour of two devices placed in series in an electrical network, with a short-circuit downstream circuit-breaker. It has two basic principles: First, discrimination which is an increasing requirement of low voltage electrical distribution systems. Second, which is less well known: cascading, which consists of installing a device, whose breaking capacity is less than the three-phase short-circuit current at its terminals and helped by main circuit-breaker. The important advantage of cascading is to be able to install at a branch circuit-breaker of a lesser performance without endangering the safety of the installation for more economical usage. To determine and guarantee co-ordination between two circuit breakers, it is necessary to carry out a theoretical approach, first, and then confirm the results by means of standard tests. This is illustrated in appendix A of IEC 947-2.

• 한국전자파학회논문지
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• 제25권1호
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• pp.47-52
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• 2014

본 논문에서는 대면적 정전식 터치스크린 구동 회로를 설계하기 위하여 여러 가지 터치스크린 패널 구조의 회로 모델을 제안하고, 그 모델의 사용 가능한 주파수 영역을 분석하였다. 터치스크린 패널 한 개 셀의 2D EM 시뮬레이션 결과를 이용한 전체 패널의 circuit 시뮬레이션을 통하여, 23인치 대면적 패널의 가장 긴 채널과 짧은 채널을 5개의 RC 소자의 회로 모델로 근사하였다. EM/circuit 시뮬레이션과 5개 소자의 RC 모델의 S 파라미터 비교를 통해, 5개 소자 모델이 130 kHz까지 10도 이내의 채널 위상 차이를 가지는 것을 확인하였다. 7개 RC 소자를 사용한 모델을 통하여 10도 이내의 채널 위상 차이를 가지는 모델의 주파수 영역을 200 kHz까지 확장하였다.

• 한국소음진동공학회논문집
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• 제20권4호
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• pp.397-404
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• 2010

The use of equivalent circuit models of piezoelectric energy harvesters is inevitable when power circuitry including rectifying and smoothing circuit elements is connected to them for evaluating DC electrical outputs. This is because it is difficult to incorporate the electro-mechanical coupling resulting from the additional circuitry into the conventional finite element analysis. Motivated by this observation, we propose a method to accurately extract the equivalent circuit parameters by using commercially available FEM software such as ANSYS which provides three-dimensional AC piezoelectric analysis. Then the equivalent circuit can be analyzed by circuit simulators such as $SimPowerSystems^{TM}$ of MATLAB. While the previous works have estimated the circuit parameters by experimental measurements or by analytical solutions developed only for limited geometries and boundary conditions, the proposed method has no such limitation because piezoelectric energy harvesters of any shapes and boundary conditions can be treated in FEM software. For the verification of the proposed method, multi-modal AC electrical power output by using a corresponding equivalent circuit is compared with that by ANSYS. The proposed method is then shown to be very useful in the subsequent evaluation of DC electrical output which is obtained by attaching a bridge diode and a storage capacitor to a piezoelectric energy harvester.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• 유공압시스템학회논문집
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• 제5권4호
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• pp.17-25
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• 2008

This study presents an analytical model of the pneumatic circuit of an air suspension system to analyze the characteristics of vehicle height control. The analytical model was developed through the co-simulation of Simulink(air spring) and HyPneu(pneumatic circuit). Variant effective area of air spring and flow coefficients of pneumatic valves were estimated experimentally prior to the system test, and utilized in simulation. One-comer test apparatus was established using the components of commercial air suspension products. The results of simulation and experiment were so close that the proposed analytical model in this study was validated. However the frictional loss of conduit and heat dissipation which were ignored in this study need to be considered in future study. As an application example of proposed analytical model, an alternative pneumatic circuit of air suspension to conventional WABCO circuit was evaluated. The comparison of simulation results of WABCO circuit and alternative circuit show that proposed analytical model of co-simulation in this study is useful for the study of pneumatic system of automotive air suspension.

• 정보처리학회논문지A
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• 제15A권2호
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• pp.69-74
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• 2008

본 논문은 MOS 전류모드 논리회로 (MOS current-mode logic circuit)의 누설전류를 감소시키기 위해 슬립 트랜지스터 (sleep-transistor) 트랜지스터를 이용하여 저 전력 MOS 전류모드 논리회로를 구현하는 새로운 구조를 제안하였다. 슬립 트랜지스터는 누설전류를 최소화하기 위해 고 문턱전압 PMOS 트랜지스터 (high-threshold voltage PMOS transistor)를 사용하였다. $16\;{\times}\;16$ 비트 병렬 곱셈기를 제안한 구조에 적용하여 제안한 구조의 타당성을 입증하였다. 이 회로는 기존 MOS 전류모드 논리회로 구조에 비해 대기전력소모가 1/50으로 감소하였다. 이 회로는 삼성 $0.35\;{\mu}m$ 표준 CMOS 공정을 이용하여 설계하였으며, HSPICE를 이용하여 검증하였다.

• 한국실내디자인학회논문집
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• 제17권3호
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• pp.59-67
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• 2008

This study aims to find out the characteristics and the type classification of contemporary public libraries in terms of browsing circuit. In so doing, it is to analyze 21 recently built libraries by using the browsing circuit, the spatial depth and the spatial layout. The study makes use of codes derived from the concept of 'Classification' and 'Frame' suggested by a pedagogist, Basil Bernstein. As a result, it shows that two codes are phased in overseas cases. In other words, one type is a lower depth of space and a high rate of rings with the multi-layer circuits and the three-dimensional circuit of multi-centered. the other type is the higher depth of space and a low rate of rings with the single-layer circuit and the multi-layer circuit of single-centered. In domestic cases, 4 types are shown. The characteristics of layout are seen as a radial shape and the rate of rings is lower than the overseas cases. It can be said that these results are a transitional phenomenon. For browsing circuit, domestic public libraries would be adapted to the three-dimensional circuit of multi-centered, a lower depth of space and a high rate of rings. By instructions of this plan, the real meaning of a public library will be come true.