• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.11
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• pp.746-754
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• 2016

Smart healthcare systems, a convergent industry based on information and communications technologies (ICT), has emerged from personal health management to remote medical treatment as a distinguished industry. The smart healthcare environment provides technology to deliver vital information, such as pulse rate, body temperature, health status, and so on, from wearable devices to the hospital network where the physician is located. However, since it deals with the patient's personal medical information, there is a security issue for personal information management, and the system may be vulnerable to cyber-attacks in wireless networks. Therefore, this study focuses on a key-development and device-management system to generate keys in the smart environment to safely manage devices. The protocol is designed to provide safe communications with the generated key and to manage the devices, as well as the generated key. The security level is analyzed against attack methods that may occur in a healthcare environment, and it was compared with existing key methods and coding capabilities. In the performance evaluation, we analyze the security against attacks occurring in a smart healthcare environment, and the security and efficiency of the existing key encryption method, and we confirmed an improvement of about 15%, compared to the existing cipher systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.6
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• pp.1301-1308
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• 2018

90/150 CA which are used as key generators of the cipher system have more randomness than LFSRs, but synthesis methods of 90/150 CA are difficult. Therefore, 90/150 CA synthesis methods have been studied by many researchers. In order to synthesize a suitable CA, the analysis of the characteristic polynomial of 90/150 CA should be preceded. In general, the characteristic of polynomial ${\Delta}_n$ of n cell 90/150 CA is obtained by using ${\Delta}_{n-1}$ and ${\Delta}_{n-2}$. Choi et al. analyzed $H_{2^n}(x)$ and $H_{2^n-1}(x)$, where $H_k(x)$ is the characteristic polynomial of k cell 90/150 CA with state transition rule <$10{\cdots}0$>. In this paper, we propose an efficient method to obtain $H_n(x)$ from $H_{n-1}(x)$ and an efficient algorithm to obtain $H_{2^n+i}(x)$ and $H_{2^n-i}(x)$ ($1{\leq}i{\leq}2^{n-1}$) from $H_{2^n}(x)$ by using this method.