• Journal of the Microelectronics and Packaging Society
• /
• v.18 no.4
• /
• pp.49-53
• /
• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.

• Journal of the Microelectronics and Packaging Society
• /
• v.7 no.2
• /
• pp.47-53
• /
• 2000

The fluxless wetting properties of TSM-coated glass substrate were evaluated by the wetting balance method. We could estimate the wettability of the TSM with new parameters obtained from the wetting balance test for one side-coated specimen. It was more effective in wetting to use Cu as a wetting layer and Au as a protection layer than to use Au itself as a wetting layer. The SnSb solder showed better wettability than SnAg, SnBi, and SnIn solders. The contact angle of the one side-coated glass substrate to the Pb-free solders could be calculated from the farce balance equation by measuring the static force and the tilt angle.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.3
• /
• pp.9-14
• /
• 2012

Robust power delivery and distribution are considered one of the major challenges in electronic devices today. As a technology develops (i.e. frequency and complexity, increase and size decreases), both power density and power supply noise increase, and voltage supply margin decreases. In addition, thermal problem is induced due to high power and poor power distribution. Until now most of studies to improve power delivery and distribution have been focused on device circuit or system architecture designs. Interconnect process technologies to resolve power delivery issues have not greatly been explored so far, but recently it becomes of great interest as power increases and voltage specification decreases in a smaller chip size.

• Transactions of the Korean Society of Mechanical Engineers
• /
• v.18 no.8
• /
• pp.2158-2166
• /
• 1994

In order to understand the package crack emanating from the edge of leadframe after the delamination between leadframe and epoxy molding compound in an electronic packaging of surface mounting type, the M-integral and J-integral in fracture mechanics are obtained. The effects of geometry, material properties and molding process temperature on the package crack are investigated taking into account the temperature dependence of the material properties, which simulates a more realistic condition. If the temperature dependence of the material properties is considered the result of analysis conforms with observations that the crack is kinked at between 50 and 65 degree. However, in case of constant material properties at the room temperature it is found that the J-integral is underestimated and the kink crack angle is different form the observation. The effects of the material properties and molding process temperature on J-integral and crack angle are less significant that the chip size for the cases considered here. It is suggested that the geometric factors such as ship size, leadframe size are to be well designed in order to prevent(or control) the occurrence and propagation of the package crack.

• Transactions of the Korean Society of Mechanical Engineers
• /
• v.18 no.8
• /
• pp.2139-2157
• /
• 1994

In order to understand the delamination between leadframe and epoxy molding compound in an electronic packaging of surface mounting type, the stress intensity factor, T-stress and J-integral in fracture mechanics are obtained. The effects of geometry, material properties and molding process temperature on the delamination are investigated taking into account the temperature dependence of the material properties, which simulates as more realistic condition. As the crack length increases the J-integral increases, which suggest that the crack propagates if it starts growing from the small size. The effects of the material properties and molding process temperature on stress intensity factor, T-stress is and J-integral are less significant than the chip size for the practical cases considered here. The T-stress is negative in all eases, which is in agreement with observation that interfacial crack is not kinked until the crack approaches the edge of the leadframe.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2003.11a
• /
• pp.24-24
• /
• 2003

Research activity in the III-V nitrides materials system has increased markedly in the past several years ever since high-brightness blue light-emitting diodes (LEDs) became commercially available. Despite of excellent optical properties of the GaN, however, inherently poor thermal property of the sapphire used as a substrate material n these devices may lead to thermal degradation of devices, especially during their high power operation. Therefore, dependable thermal analysis and packaging schemes of GaN-based LEDs are necessary for solid lighting applications under high power operation. In this paper, emphasis will be placed upon thermal design of GaN-based LEDs. Thermal measurements of LEDs on chip and packaging scale were performed using the liquid crystal thermographic technology and micro thermocouples for different bias conditions. By a series of optical arrangement, hot spots with specific transition temperatures were obtained with increasing input power. Thermal design of LEDS was made using the finite element method and analytical unit temperature profile approach with optimal boundary conditions. The experimental results were compared to the simulated data and the results agree well enough for the establishment of dependable prediction of thermal behavior in these devices. The paper will present a more detailed understanding of the thermal analysis of the GaN-based blue and white LEDs for high power applications.

• Proceedings of the KWS Conference
• /
• 2002.10a
• /
• pp.439-449
• /
• 2002

This paper reviews our recent research works on the interconnection technologies in electronic packaging and assembly. At the aspect of advanced joining methods, laser-ultrasonic fluxless soldering technology was proposed. The characteristic of this technology is that the oxide film was removed through the vibration excitated by high frequency laser change in the molten solder droplet. Application researches of laser soldering technology on solder bumping of BGA packages were carried out. Furthermore, interfacial reaction between SnPb eutectic solder and Au/Ni/Cu pad during laser reflow was analyzed. At the aspect of soldered joints' reliability, the system for predicting and analyzing SMT solder joint shape and reliability(PSAR) has been designed. Optimization design method of soldered joints' structure was brought forward after the investigation of fatigue failure of RC chip devices and BGA packages under temperature cyclic conditions with FEM analysis and experimental study. At the aspect of solder alloy design, alloy design method based on quantum was proposed. The macroproperties such as melting point, wettability and strength were described by the electron parameters. In this way, a great deal of the experimental investigations was replaced, so as to realize the design and research of any kinds of solder alloys with low cost and high efficiency.

• Journal of the Microelectronics and Packaging Society
• /
• v.11 no.2 s.31
• /
• pp.11-16
• /
• 2004

Electronic devices are getting smaller due to integration of electronic chip, and heat generated in electronic devices can cause loss of performance and/or reliability of the devices. In this research, metals such as gold, nickel and copper are plated onto a porous membrane by electroless plating method to make an efficient micro-heatsinks. Electroless plating includes sensitization and activation steps in pre-treatment steps. A polycarbonate(PC) membrane was sensitizied, activated and deposited in each metal solution for plating. Among manufactured microfibrils, heat transfer and radiation properties of Ni-microfibril with high surface area were more effective than those of $Au^-$ and Cu-microfibril.

• Journal of the Microelectronics and Packaging Society
• /
• v.22 no.2
• /
• pp.5-9
• /
• 2015

Thermal management becomes serious in 3D stacked IC because of higher heat flux, increased power generation, extreme hot spot, etc. In this paper, we reviewed the recent developments of thermal management for 3D stacked IC which is a promising candidate to keep Moore's law continue. According to experimental and numerical simulation results, Cu TSV affected heat dissipation in a thin chip due to its high thermal conductivity and could be used as an efficient heat dissipation path. Other parameters like bumps, gap filling material also had effects on heat transfer between stacked ICs. Thermal aware circuit design was briefly discussed as well.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.4
• /
• pp.45-50
• /
• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.