• Journal of the Microelectronics and Packaging Society
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• v.7 no.2
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• pp.55-62
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• 2000

The wetting balance test was performed in an attempt to estimate the wetting properties of the UBM-coated Si-wafer on one side to the Sn-Pb solder. The wetting curves of the one and both side-coated UBM layers had the similar shape and the parameters characterizing the curve shape showed the similar transition tendency to the temperature. The wetting property estimation was possible with the new wettability indices from the wetting curves of one side-coated specimen; $F_{min}$, $F_{s}t_{s}$ and $t_s$. For UBM of Si-chip, Au/Cu/Cr UBM was better than Au/Ni/Ti in the point of wetting time. The contact angle of the one side coated Si-plate to the Sn-Pb solder could be calculated from the force balance equation by measuring the static state force and the tilt angle.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.71-76
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• 2015

Recently, light emitting diodes (LEDs) have been studied to improve their efficiencies for the uses in various fields. Particularly in the aspect of chip structure, via hole type vertical LED chip is developed for improvement of light output power, and heat dissipations. However, current vertical type LEDs have still drawback, which is current concentration around the n-contact holes. In this research, to solve this phenomenon, we introduced isolation layer under n-contact electrodes. With this sub-electrode, even though the active area was decreased by about 2.7% compared with conventional via-hole type vertical LED, we could decrease the forward voltage by 0.2 V and wall-plug efficiency was improved approximately 4.2%. This is owing to uniform current flow through the area of n-contact.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.33-37
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• 2011

In this study, the degradation mechanism of mounted chip resistors with Ag-epoxy isotropic conductive adhesives (ICAs) under the humidity exposure ($85^{\circ}C$/85%RH) was examined by electrical resistance change and microstructural study. The effect of the chloride content in Ag-epoxy ICA on joint stability was also examined. The increasing range of the electrical resistance in the typical ICA joint was greater than that in the low Cl content ICA joint. In the case of the typical ICA joint, Sn oxides such as SnO, $SnO_2$, and Sn-Cl-O were formed inhomogeneously on the surface of the Sn plating during the $85^{\circ}C$/85%RH test. In contrast, no Sn-Cl-O was found in the low Cl content ICA joint during the $85^{\circ}C$/85%RH. It is suggested that Cl in Ag-epoxy ICA accelerate the electrical degradation of Sn plated chip components joined with Ag-epoxy ICA.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.11-17
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• 2010

The electromigration phenomenon in lead-free flip-chip solder joint has been one of the serious problems. To understand the mechanism of this phenomenon, the crystallographic orientation of Sn grain in the Sn-Ag-Cu solder bump has been analyzed. Different time to failure and different microstructural changes were observed in the all test vehicle and bumps, respectively. Fast failure and serious dissolution of Cu electrode was observed when the c-axis of Sn grain parallel to electron flow. On the contrary of this, slight microstructural changes were observed when the c-axis of Sn perpendicular to electron flow. In addition, underfill could enhance the electromigration reliability to prevent the deformation of solder bump during EM test.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.27-31
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• 2015

Thermal management becomes a key technology as the power density of high performance and high density devices increases. Conventional heat sink or TIM methods will be limited to resolve thermal problems of next-generation IC devices. Recently, to increase heat flux through high powered IC devices liquid cooling system has been actively studied. In this study a chip-level liquid cooling system with TSV and microchannel was fabricated on Si wafer using DRIE process and analyzed the cooling characteristics. Three different TSV shapes were fabricated and the effect of TSV shapes was analyzed. The shape of liquid flowing through microchannel was observed by fluorescence microscope. The temperature differential of liquid cooling system was measured by IR microscope from RT to $300^{\circ}C$.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.1-4
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• 2009

This work shows how the adoption of a dual-dicing process for silicon wafer separation affects the thermal-cycling reliability (i.e. $-65^{\circ}C$ to $150^{\circ}C$) of the semiconductor devices utilizing lead-on-chip (LOC) die attach technique. In-situ examinations show that conventional single-dicing process directly attacks the edge region of diced devices but dual-dicing process effectively protects the edge region of diced devices from dicing-induced mechanical damage. Probably, this is because the preferential and sacrificial fracture of notched regions induced on the active surface of wafers saves the edge regions. It was also investigated through thermal-cycling tests that the number of thermal-cycling induced failures is much lower at the dual-dicing process than the single-dicing process.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.43-55
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• 2003

As the development of If industries and their electronic device manufacturing technology have been accelerated recently, the request for electronic devices with small size, light weight, and high performance has been inducing that electronic package and substrate (PCB) companies have to develop substrates with low cost, high dense I/O, excellent thermal properties and electrical properties. Therefore, world-wide chip makers have been setting their own severe reliability standards and requiring their suppliers to keep specification and to develop green, high frequency and high-performing substrates. Because properties of substrates are dependent mainly on their constituent materials, the application of them showing superior properties is expected to satisfy the customer's requirement. Therefore, substrate companies should ensure the superiority of materials and assure their competitive capability of substrates by analyzing the latest trends of technology and properties of the materials.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.21-30
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• 2018

Driven by the recent energy saving trend, conventional silicon based power conversion modules are being replaced by modules using silicon carbide. Previous papers have focused mainly on the electrical advantages of silicon carbide semiconductors that can be used to design switching devices with much lower losses than conventional silicon based devices. However, no systematic study of their thermomechanical reliability in power conversion modules using finite element method (FEM) simulation has been presented. In this paper, silicon and silicon carbide based power devices with three-phase switching were designed and compared from the viewpoint of thermomechanical reliability. The switching loss of power conversion module was measured by the switching loss evaluation system and measured switching loss data was used for the thermal FEM simulation. Temperature and stress/strain distributions were analyzed. Finally, a thermal fatigue simulation was conducted to analyze the creep phenomenon of the joining materials. It was shown that at the working frequency of 20 kHz, the maximum temperature and stress of the power conversion module with SiC chips were reduced by 56% and 47%, respectively, compared with Si chips. In addition, the creep equivalent strain of joining material in SiC chip was reduced by 53% after thermal cycle, compared with the joining material in Si chip.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.281-287
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• 2005

in-situ electromigration test was carried out for edge drift lines of eutectic SnPb solder using Scanning Electron Microscopy (SEM). The electromigration test for the eutectic SnPb solder sample was conducted at temperature of $90^{\circ}C$ and the current density of $6{\times}10^4A/cm^2$. Edge drift at cathode and hillock growth at anode were observed in-situ in a SEM chamber during electromigration test. It was clearly revealed that eutectic SnPb solder lines has an incubation stage before void formation during electromigration test, which seemed to be related to the void nucleation stage of flip chip solder electromigration behaviors.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.2 s.39
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• pp.1-7
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• 2006

In this paper, warpage magnitude and shape of printed-circuit board in case that properties of core and thickness of solder resist are varied are investigated. The cause of warpage is coefficient of thermal expansion differences of stacked materials. Therefore, we need small difference of coefficient of thermal expansion that laminated material, and need to decrease asymmetric of top side and bottom side in structure shape. Also, we can control occurrence of warpage heightening hardness of core in laminated material. Composite material that make core are exploited in connection with the structural bending twisting coupling resulting from directional properties of fiber reinforced composite materials and from ply stacking sequence. If we use such characteristic, we can control warpage with change of material properties. In this paper, warpage of two layer stacked chip scale package is investigated, and evaluate improvement result using an experiment and finite element method tool.