• Title/Summary/Keyword: Chip-packaging

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AlN Based RF MEMS Tunable Capacitor with Air-Suspended Electrode with Two Stages

  • Cheon, Seong J.;Jang, Woo J.;Park, Hyeon S.;Yoon, Min K.;Park, Jae Y.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.1
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    • pp.15-21
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    • 2013
  • In this paper, a MEMS tunable capacitor was successfully designed and fabricated using an aluminum nitride film and a gold suspended membrane with two air gap structure for commercial RF applications. Unlike conventional two-parallel-plate tunable capacitors, the proposed tunable capacitor consists of one air suspended top electrode and two fixed bottom electrodes. One fixed and the top movable electrodes form a variable capacitor, while the other one provides necessary electrostatic actuation. The fabricated tunable capacitor exhibited a capacitance tuning range of 375% at 2 GHz, exceeding the theoretical limit of conventional two-parallel-plate tunable capacitors. In case of the contact state, the maximal quality factor was approximately 25 at 1.5 GHz. The developed fabrication process is also compatible with the existing standard IC (integrated circuit) technology, which makes it suitable for on chip intelligent transceivers and radios.

Interconnection Process and Electrical Properties of the Interconnection Joints for 3D Stack Package with $75{\mu}m$ Cu Via ($75{\mu}m$ Cu via가 형성된 3D 스택 패키지용 interconnection 공정 및 접합부의 전기적 특성)

  • Lee Kwang-Yong;Oh Teck-Su;Won Hye-Jin;Lee Jae-Ho;Oh Tae-Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.12 no.2 s.35
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    • pp.111-119
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    • 2005
  • Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

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High-temperature Semiconductor Bonding using Backside Metallization with Ag/Sn/Ag Sandwich Structure (Ag/Sn/Ag 샌드위치 구조를 갖는 Backside Metallization을 이용한 고온 반도체 접합 기술)

  • Choi, Jinseok;An, Sung Jin
    • Journal of the Microelectronics and Packaging Society
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    • v.27 no.1
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    • pp.1-7
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    • 2020
  • The backside metallization process is typically used to attach a chip to a lead frame for semiconductor packaging because it has excellent bond-line and good electrical and thermal conduction. In particular, the backside metal with the Ag/Sn/Ag sandwich structure has a low-temperature bonding process and high remelting temperature because the interfacial structure composed of intermetallic compounds with higher melting temperatures than pure metal layers after die attach process. Here, we introduce a die attach process with the Ag/Sn/Ag sandwich structure to apply commercial semiconductor packages. After the die attachment, we investigated the evolution of the interfacial structures and evaluated the shear strength of the Ag/Sn/Ag sandwich structure and compared to those of a commercial backside metal (Au-12Ge).

Printing Morphology and Rheological Characteristics of Lead-Free Sn-3Ag-0.5Cu (SAC) Solder Pastes

  • Sharma, Ashutosh;Mallik, Sabuj;Ekere, Nduka N.;Jung, Jae-Pil
    • Journal of the Microelectronics and Packaging Society
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    • v.21 no.4
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    • pp.83-89
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    • 2014
  • Solder paste plays a crucial role as the widely used joining material in surface mount technology (SMT). The understanding of its behaviour and properties is essential to ensure the proper functioning of the electronic assemblies. The composition of the solder paste is known to be directly related to its rheological behaviour. This paper provides a brief overview of the solder paste behaviour of four different solder paste formulations, stencil printing processes, and techniques to characterize solder paste behaviour adequately. The solder pastes are based on the Sn-3.0Ag-0.5Cu alloy, are different in their particle size, metal content and flux system. The solder pastes are characterized in terms of solder particle size and shape as well as the rheological characterizations such as oscillatory sweep tests, viscosity, and creep recovery behaviour of pastes.

Magnetic and Thermal Evaluation of a Magnetic Tunneling Junction Current Sensor Package

  • Rhod, Eduardo;Peter, Celso;Hasenkamp, Willyan;Grion, Agner
    • Journal of the Microelectronics and Packaging Society
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    • v.23 no.4
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    • pp.49-55
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    • 2016
  • Nowadays there are magnetic sensors in a wide variety of equipment such as computers, cars, airplanes, medical and industrial instruments. In many of these applications the magnetic sensors offer safe and non-invasive means of detection and are more reliable than other technologies. The electric current in a conductor generates a magnetic field detected by this type of sensor. This work aims to define a package dedicated to an electrical current sensor using a MTJ (Magnetic Tunnel Junction) as a sensing device. Four different proposals of packaging, three variations of the chip on board (CoB) package type and one variation of the thin small outline package (TSOP) were analyzed by COMSOL modeling software by simulating a brad range of current injection. The results obtained from the thermal and magnetic analysis has proven to be very important for package improvements, specially for heat dissipation performance.

Fabrication of Porous Cu Layers on Cu Pillars through Formation of Brass Layers and Selective Zn Etching, and Cu-to-Cu Flip-chip Bonding (황동층의 형성과 선택적 아연 에칭을 통한 구리 필라 상 다공성 구리층의 제조와 구리-구리 플립칩 접합)

  • Wan-Geun Lee;Kwang-Seong Choi;Yong-Sung Eom;Jong-Hyun Lee
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.4
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    • pp.98-104
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    • 2023
  • The feasibility of an efficient process proposed for Cu-Cu flip-chip bonding was evaluated by forming a porous Cu layer on Cu pillar and conducting thermo-compression sinter-bonding after the infiltration of a reducing agent. The porous Cu layers on Cu pillars were manufactured through a three-step process of Zn plating-heat treatment-Zn selective etching. The average thickness of the formed porous Cu layer was approximately 2.3 ㎛. The flip-chip bonding was accomplished after infiltrating reducing solvent into porous Cu layer and pre-heating, and the layers were finally conducted into sintered joints through thermo-compression. With reduction behavior of Cu oxides and suppression of additional oxidation by the solvent, the porous Cu layer densified to thickness of approximately 1.1 ㎛ during the thermo-compression, and the Cu-Cu flip-chip bonding was eventually completed. As a result, a shear strength of approximately 11.2 MPa could be achieved after the bonding for 5 min under a pressure of 10 MPa at 300 ℃ in air. Because that was a result of partial bonding by only about 50% of the pillars, it was anticipated that a shear strength of 20 MPa or more could easily be obtained if all the pillars were induced to bond through process optimization.

Process Capability Optimization of a LED Die Bonding Using Response Surface Analysis (반응표면분석법을 이용한 LED Die Bonding 공정능력 최적화)

  • Ha, Seok-Jae;Cho, Yong-Kyu;Cho, Myeong-Woo;Lee, Kwang-Cheol;Choi, Won-Ho
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.10
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    • pp.4378-4384
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    • 2012
  • In LED chip packaging, die bonding is a very important process which fixes the LED chip on the lead frame to provide enough strength for the next process. This paper focuses on the process optimization of a LED die bonding, which attaches small zener diode chip on PLCC LED package frame, using response surface analysis. Design of experiment (DOE) of 5 factors, 3 levels and 5 responses are considered, and the results are investigated. As the results, optimal conditions those satisfy all response objects can be derived.

Design and fabrication of condenser microphone with rigid backplate and vertical acoustic holes using DRIE and wafer bonding technology (기판접합기술을 이용한 두꺼운 백플레이트와 수직음향구멍을 갖는 정전용량형 마이크로폰의 설계와 제작)

  • Kwon, Hyu-Sang;Lee, Kwang-Cheol
    • Journal of Sensor Science and Technology
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    • v.16 no.1
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    • pp.62-67
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    • 2007
  • This paper presents a novel MEMS condenser microphone with rigid backplate to enhance acoustic characteristics. The MEMS condenser microphone consists of membrane and backplate chips which are bonded together by gold-tin (Au/Sn) eutectic solder bonding. The membrane chip has 2.5 mm${\times}$2.5 mm, $0.5{\mu}m$ thick low stress silicon nitride membrane, 2 mm${\times}$2 mm Au/Ni/Cr membrane electrode, and $3{\mu}m$ thick Au/Sn layer. The backplate chip has 2 mm${\times}$2 mm, $150{\mu}m$ thick single crystal silicon rigid backplate, 1.8 mm${\times}$1.8 mm backplate electrode, and air gap, which is fabricated by bulk micromachining and silicon deep reactive ion etching. Slots and $50-60{\mu}m$ radius circular acoustic holes to reduce air damping are also formed in the backplate chip. The fabricated microphone sensitivity is $39.8{\mu}V/Pa$ (-88 dB re. 1 V/Pa) at 1 kHz and 28 V polarization voltage. The microphone shows flat frequency response within 1 dB between 20 Hz and 5 kHz.

Microfabrication of Microwave Transceivers for On-Chip Near-Field Electromagnetic Shielding Characterization of Electroplated Copper Layers (극소형 전자기파 송수신기의 제작 및 전기도금된 구리박막의 칩단위 근접 전자기장 차폐효과 분석)

  • Gang, Tae-Gu;Jo, Yeong-Ho
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.25 no.6
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    • pp.959-964
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    • 2001
  • An experimental investigation on the near-field electromagnetic loss of thin copper layers has been presented using microfabricated microwave transceivers for applications to multi-chip microsystems. Copper layers in the thickness range of 0.2$\mu$m∼200$\mu$m have been electroplated on the Pyrex glass substrates. Microwave transceivers have been fabricated using the 3.5mm$\times$3.5mm nickel microloop antennas, electroformed on the silicon substrates. Electromagnetic radiation loss of the copper layers placed between the microloop transceivers has been measured as 10dB∼40dB for the wave frequency range of 100MHz∼1GHz. The 0.2$\mu$m-thick copper layer provides a shield loss of 20dB at the frequencies higher than 300MHz, whereas showing a predominant decreases of shield loss to 10dB at lower frequencies. No substantial increase of the shield effectiveness has been found for the copper shield layers thicker that 2 $\mu$m.

Effects of Sputtering Conditions of TiW Under Bump Metallurgy on Adhesion Strength of Au Bump Formed on Al and SiN Films (Al 및 SiN 박막 위에 형성된 TiW Under Bump Metallurgy의 스퍼터링 조건에 따른 Au Bump의 접착력 특성)

  • Jo, Yang-Geun;Lee, Sang-Hee;Kim, Ji-Mook;Kim, Hyun-Sik;Chang, Ho-Jung
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.3
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    • pp.19-23
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    • 2015
  • In this study, two types of Au/TiW bump samples were fabricated by the electroplating process onto Al/Si and SiN/Si wafers for the COG (Chip On Glass) packaging. TiW was used as the UBM (Under Bump Metallurgy) material of the Au bump and it was deposited by a sputtering method under the sputtering powers ranges from 500 to 5000 Watt. We investigated the delamination phenomenas for the prepared samples as a function of the input sputtering powers. The stable interfacial adhesion condition was found to be 1500 Watt in sputtering power. In addition, the SAICAS (Surface And Interfacial Cutting Analysis System) measurement was used to find the adhesion strength of Au bumps for the prepared samples. TiW UBM films were deposited at the 1500 Watt sputtering power. As a results, there was a similar adhesion strengths between TiW/Au interfacial films on Al/Si and SiN/Si wafers. However, the adhesion strength of TiW UBM sputtering films on Al and SiN under films were 2.2 times differences, indicating 0.475 kN/m for Al/Si wafer and 0.093 kN/m for SiN/Si wafer, respectively.