• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권7호
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• pp.339-343
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• 2006

In this study, the variations of the important characteristics of solenoid-type RF chip inductors utilizing a low-loss A1203 core material on inductor dimensions were investigated systematically. Four dimensions of the chip inductors fabricated in this work were $1.0\times0.5\times0.5mm^3,\;1.5\times1.0\times0.7mm^3,\;2.1\times1.5\times1.0mm^3,\;and\;2.4\times2.0\times1.4mm^3$ and copper (Cu) wire with $40{\mu}m$ diameter was used as the coils. High frequency characteristics of the inductance, quality factor, and impedance of developed inductors as a function of inductor dimensions were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). It was observed that the developed inductors with the number of turns of 6 have the inductance (L) of 12 to 82 nH and exhibit the self-resonant frequency (SRE) of 3.6 to 1.2 GHz. The SRF of inductors decreases with increasing the inductor size while the L increases with the inductor size. The smallest inductors of $1.0\times0.5\times0.5mm^3$ exhibited the L of 12 nH, SRF of 3.6 GHz, and the quality factor of 67 near the frequency of 1.1 GHz. The calculated data predicted the high-frequency data of the L, and Q of the developed inductors well.

• 한국항해항만학회지
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• 제27권2호
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• pp.217-221
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• 2003

본 논문에서는 새로운 형태의 CSP (chip site package)를 이용하여 정합소자 린 바이어스소자를 MMIC상에 완전집적한 Ku/K밴드 광대역 증폭기 MMIC에 관하여 보고한다. 새로운 형태의 CSP에 대해서는 이방성 도전필름인 ACF (anisotropic conductive film)을 이용하였으며, 그 결과 MMIC 패키지 프로세스가 간략화 되었고, CSP MMIC의 저 가격화가 실현되었다. MMIC상에 집적하기 위한 DC 바이어스 용량소자로서는 고유전율의 STO (SrTiO3) 필름 커패시터가 이용되었다. 제작된 CSP MMIC는 광대역 RF동작특성 (12-24 GHz에서 12.5$\pm$1.5 dB의 이득치, -6 dB이하의 반사계수, 18.5$\pm$1.5 dBm의 PldB) 을 보였다. 본 논문은 K 또는 Ku 밴드의 주파수대역에 있어서의 완전집적화 CSP MMIC에 관한 최초의 보고이다.

• 한국정보통신학회논문지
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• 제25권9호
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• pp.1158-1165
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• 2021

본 논문은 메모리의 사이즈를 줄이기 위해 Pooling Layer가 MAC에 통합된 구조의 최적화된 CNN가속기를 설계하는 것을 제안한다. 메모리와 데이터 전달 회로의 최소화를 위해 MNIST를 이용하여 학습된 32bit 부동소수점 가중치 값을 8bit로 양자화하여 사용하였다. 가속기칩 크기의 최소화를 위해 MNIST용 CNN 모델을 1개의 Convolutional layer, 4*4 Max Pooling, 두 개의 Fully connected layer로 축소하였고 모든 연산에는근사화 덧셈기와 곱셈기가 들어간 특수 MAC을 사용한다. Convolution 연산과 동시에 Pooling이 동작하도록 설계하여 내장 메모리를 94% 만큼 축소하였으며, pooling 연산의 지연 시간을 단축했다. 제안된 구조로 MNIST CNN 가속기칩을 TSMC 65nm GP 공정으로 설계한 결과 기존 연구결과의 절반 크기인 0.8mm x 0.9mm = 0.72mm²의 초소형 가속기 설계 결과를 도출하였다. 제안된 CNN 가속기칩의 테스트 결과 94%의 높은 정확도를 확인하였으며, 100MHz 클럭 사용시 MNIST 이미지당 77us의 빠른 처리 시간을 획득하였다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.763-768
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• 2005

Bare-chip packaging becomes more popular along with the miniaturization of IT components. In this paper, we have studied flip-chip process, and developed automated bonding system. Among the several bonding method, NCP bonding is chosen and batch-type equipment is manufactured. The dual optics and vision system aligns the chip with the substrate. The bonding head equipped with temperature and force controllers bonds the chip. The system can be easily modified for other bonding methods such as ACF In bonding process, the bonding forte and temperature are known as the most dominant bonding parameters. A parametric study is performed for these two parameters. For the test sample, we used standard flip-chip test kit which consists of FR4 boards and dummy flip-chips. The bonding test was performed fur two types of flip-chips with different chip size and lead pitch. The bonding temperatures are chosen between $25^{\circ}C\;to\;300^{\circ}C$. The bonding forces are chosen between 5N and 300N. The bonding strength is checked using bonding force tester. After the bonding force test, the samples are examined by microscope to determine the failure mode. The relations between the bonding strength and the bonding parameters are analyzed and compared with bonding models. Finally, the most suitable bonding condition is suggested in terms of temperature and force.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 2nd Korea-Japan Advanceed Semiconductor Packaging Technology Seminar
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• pp.39-45
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• 2000

A small camera module fabricated by including bare chip bonding methods is utilized to realize advanced mobile devices. One of the driving forces is the TOG (Tape On Glass) bonding method which reduces the packaging size of the image sensor clip. The TOG module is a new thinner and smaller image sensor module, using flip chip interconnection method with the ACP (Anisotropic Conductive Paste). The TOG production process was established by determining the optimum bonding conditions for both optical glass bonding and image sensor clip bonding lo the flexible PCB. The bonding conditions, including sufficient bonding margins, were studied. Another bonding method is the flip chip bonding method for DSP (Digital Signal Processor) chip. A new AC\ulcorner was developed to enable the short resin curing time of 10 sec. The bonding mechanism of the resin curing method was evaluated using FEM analysis. By using these flip chip bonding techniques, small camera module was realized.

• ETRI Journal
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• 제30권3호
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• pp.347-354
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• 2008

In this paper, the design of a low-power 512-bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low-power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage-up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 ${\mu}m$ EEPROM process. Power dissipation is 32.78 ${\mu}W$ in the read cycle and 78.05 ${\mu}W$ in the write cycle. The layout size is 449.3 ${\mu}m$ ${\times}$ 480.67 ${\mu}m$.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2002년도 춘계학술대회 논문집
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• pp.302-307
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• 2002

In end milling process, the undeformed chip section area and cutting forces vary periodically with phase change of the tool. However, the real undeformed chip section area deviates from the geometrically ideal one owing to cutter runout and tool shape error. In this study, a method of estimating the real undeformed chip section area which reflects cutter runout and tool shape error was presented during up-end milling of Inconel 718 using measured cutting forces. The specific cutting resistance, K. and $K_t$ are defined as the radial and tangential cutting forces divided by the modified chip section area. Both of $K_r$, and $K_t$ values become smaller as the helix angle increases from $30^\circ$ to $40^\circ$ Whereas they become larder as the helix angle increases from $40^\circ$ to $50^\circ$. On the other hand, the $K_r$, and $K_t$ values show a tendency to decrease with increase of the modified chip section area and this tendency becomes distinct with smaller helix angle.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2003년도 춘계학술대회논문집
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• pp.427-733
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• 2003

Adiabatic shear bands have been observed in the serrated chip during high strain rate metal cutting process of medium carbon steel and titanium alloy. The recent microscopic observations have shown that dynamic recrystallization occurs in the narrow adiabatic shear bands. However the conventional flow stress models such as the Zerilli-Armstrong model and the Johnson-Cook model, in general, do not predict the occurrence of dynamic recrystallization (DRX) in the shear bands and the thermal softening effects accompanied by DRX. In the present study, a strain hardening and thermal softening model is proposed to predict the adiabatic shear localized chip formation. The finite element analysis (FEA) with this proposed flow stress model shows that the temperature of the shear band during cutting process rises above 0.5T$\sub$m/. The simulation shows that temperature rises to initiate dynamic recrystallization, dynamic recrystallization lowers the flow stress, and that adiabatic shear localized band and the serrated chip are formed. FEA is also used to predict and compare chip formations of two flow stress models in orthogonal metal cutting with AISI 1045. The predictions of the FEA agreed well with the experimental measurements.

• Journal of information and communication convergence engineering
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• 제6권2호
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• pp.122-128
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• 2008

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

• 한국정보통신학회논문지
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• 제7권6호
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• pp.1115-1122
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• 2003

본 논문에서는 Blluetooth 주파수 대역 2.402 ∼ 2.480GHz 에서 동작하는 마이크로 칩 안테나를 제작하였다. 안테나는 54mm${\times}419mm${\times}40.8mm의 bluetooth PCB 크기와 11mm${\times}44mm${\times}41.6mm의 칩 크기를 갖는다. 설계 제작 된 Bluetooth용 칩 안테나는 2.45GHz 의 중심주파수에서 10.71 %의 대역폭을 갖고, 임의의 급전점 변화에 따라 대역폭과 공진주파수의 변화를 보였다. 또한, 칩안테나의 측정된 방사패턴에서 E-면과 H-면을 비교 분석하였다.