• 한국정밀공학회지
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• 제15권10호
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• pp.128-139
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• 1998

In this paper, a finite element method for predicting the temperature and stress distributions in micro-machining is presented. The work material is oxygen-free-high-conductivity copper(OFHC copper) and its flow stress is taken as a function of strain, strain rate and temperature in order to reflect realistic behavior in machining process. From the simulation, a lot of information on the micro-machining process can be obtained; cutting force, cutting temperature, chip shape, distributions of temperature and stress, etc. The calculated cutting force was found to agree with the experiment result with the consideration of friction characteristics on chip-tool contact region. Because of considering the tool edge radius, this cutting model using the finite element method can analyze the micro-machining with the very small depth of cut, almost the same size of tool edge radius, and can observe the 'size effect' characteristic. Also the effects of temperature and friction on micro-machining were investigated.

• 마이크로전자및패키징학회지
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• 제18권1호
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• pp.41-47
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• 2011

Currently, there is widespread adoption of silicon-based technologies for the implementation of radio frequency (RF) integrated passive devices (IPDs) because of their low-cost, small footprint and high performance. Also, the need for high speed data transmission and reception coupled with the ever increasing demand for mobility in consumer devices has generated a great interest in low cost devices with smaller form-factors. The UWB BPF makes use of lumped IPD technology on a silicon substrate CSMP (Chip Scale Module Package). In this paper, this filter shows 2.0 dB insertion loss and 15 dB return loss from 7.0 GHz to 9.0 GHz. To the best of our knowledge, the UWB band-pass-filter developed in this paper has the smallest size ($1.4\;mm{\times}1.2\;mm{\times}0.40\;mm$) while achieving equivalent electrical performance.

• Journal of the Korean Physical Society
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• 제73권9호
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• pp.1346-1350
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• 2018

An electrode-evaporation technology on both the top and bottom sides of the bare vertical-type single chip separated from the traditional substrate by cooling, was developed for III-nitride vertical-type single chip LEDs with thick GaN epilayer. The post-process of the cooling step was followed by sorting the bare vertical-type single chip LEDs into the holes in a pocket-type shadow mask for deposition of the electrodes at the top and bottom sides of bare vertical-type single chip LEDs without the traditional substrate for electrode evaporation technology for vertical-type single chip LEDs. The variation in size of the hole between the designed shadow mask and the deposited electrodes owing to the use of the designed pocket-type shadow mask is investigated. Furthermore, the electrical and the optical properties of bare vertical-type single chip LEDs deposited with two different shapes of n-type electrodes using the pocket-type shadow mask are investigated to explore the possibility of the e-beam evaporation method.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 추계학술대회 논문집
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• pp.323-324
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• 2008

• Transactions on Electrical and Electronic Materials
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• 제15권2호
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• pp.66-68
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• 2014

Most commercial white LED lamps use blue chip coated with yellow emitting phosphor. The use of blue excitable red and green phosphors is expected to improve the CRI. Several phosphors, such as $SrGa_2S_4:Eu^{2+}$ and $(Sr,Ba)SiO_4:Eu^{2+}$, have been suggested in the past as green components. However, there are issues of the sensitivity and stability of such phosphors. Here, we describe gallium substituted $YAG:Ce^{3+}$ phosphor, as a green emitter. YAG structures are already accepted by the industry, for their stability and efficiency. LEDs with improved CRI could be fabricated by choosing $Y_3Al_4GaO_{12}:Ce^{3+}$ (green and yellow), and $SrS:Eu^{2+}$ (red) phosphors, along with blue chip. Also, the effect of a slight change in chip wavelength is studied, for two phosphor-coated w-LEDs. The reduction in particle size of the coated phosphors also gives improved w-LED characteristics.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 3rd Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.121-145
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• 2001

Chip Size Packages (CSP) are now widely used in high speed DRAM. The major driving farce of CSP development is its superior electrical performance than that of conventional package. However, the power dissipation of high speed DRAM like DDR or RAMBUS DRAM chip reaches up to near 2W. This fact makes the thermal management methods in DRAM package be more carefully considered. In this study, the thermal performances of 3 type CSPs named $\mu-BGA$^{TM}$$ $UltraCSP^{TM}$ and OmegaCSP$^{TM}$ were measured under the JEDEC specifications and their thermal characteristics were of a simulation model utilizing CFD and FEM code. The results show that there is a good agreement between the simulation and measurement within Max. 10% of $\circledM_{ja}$. And they show the wafer level CSPs have a superior thermal performance than that of $\mu-BGA.$ Especially the analysis results show that the thermal performance of wafer level CSPs are excellent fur modulo level in real operational mode without any heat sink.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.100-103
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• 2008

본 논문에서는 AMBA 기반으로 사용될 수 있는 H.264용 Encoder Hardware 모듈(Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, Motion Estimation)을 Integration하여 설계하였다. 설계된 모듈은 한 매크로 블록당 최대 440 cycle내에 동작한다. 제안된 Encoder 구조를 검증하기 위하여 JM 9.4부터 reference C를 개발하였으며, reference C로부터 test vector를 추출하며 설계 된 회로를 검증하였다. 제안된 회로는 최대 166MHz clock에서 동작하며, 합성결과 Charterd 0.18um 공정에 램 포함 약 180만 gate 크기이다. MPW제작시 chip size $6{\times}6mm$의 크기와 208 pin의 Pakage 형태로 제작하였다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.131-135
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• 2002

본 연구에서는 개인 통신기의 핵심부품인 초소형 세라믹 칩 안테나 (SMD형) 개발의 무선회로 설계 기술, 초소형 설계기술, 표면실장기술, 소형화 SMD기술, Test기술 및 설계기반 마련 및 대외 경쟁력 있는 초소형 세라믹 칩 안테나 (SMD형) 개발의 초소형화 기술을 확보하였다. 중심주파수는 2442.5MHz(Type), 반사손실은 -l0dB이하, 정재파비는 2max, xy의 최대 이득은 -2dB 이상, size는 0.05ccmax이다.

• 한국진공학회지
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• 제17권6호
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• pp.549-554
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• 2008

수소 플라즈마 처리된 유리 기판에 스핀 코팅 시스템을 이용하여 nickel chloride를 코팅하여 단백질칩 플레이트를 제조하였다. 다양한 플라즈마 처리 시간대에서 histidine tagged 단백질의 부착 능력 특성을 연구하였다. 유리 기판 표면에서 nickel chloride와 단백질 특성을 particle size analysis를 이용하여 관찰하였고, 단백질의 부착 능력 정도를 bio imaging analyzer system으로 측정하였다. 실험 결과에 따르면, 플라즈마 처리 시간이 증가할수록 단백질 부착 능력은 감소하는 것으로 나타났다. 기판 표면에서의 단백질 부착능력 특성에 관한 mechanism은 본문의 결과 및 토의에서 논의되었다. 플라즈마 처리된 단백질칩 기판에 대한 표면 안정화는 바이오센서 시장에서 큰 관심을 끌 것으로 기대된다.

• 한국정보통신학회논문지
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• 제13권12호
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• pp.2647-2654
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• 2009

본 논문에서는 AMBA 기반으로 사용될 수 있는 H.264용 Encoder Hardware 모듈 (Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, Motion Estimation)을 Integration하여 설계하였다. 설계된 모듈은 한 매크로 블록당 최대 440 cycle내에 동작한다. 제안된 인코더 구조를 검증하기 위하여 JM 9.4부터 reference C를 개발하였으며, reference C로부터 test vector를 추출하여 설계 된 회로를 검증하였다. 제안된 회로는 최대 166MHz clock에서 동작하며, 합성결과 Charterd 0.18 um 공정에 램 포함 약 173만 gate 크기이다. MPW제작시 chip size $6{\times}6mm$의 크기와 208 pin의 Package 형태로 제작 하였다.