• 한국생산제조학회지
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• 제21권2호
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• pp.225-231
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• 2012

Drop simulations of the board level in the flip chips with solder joints have been highlighted for years, recently. Also, through the study on the life prediction of thermal fatigue in the flip chips considering underfill, its importance has been issued greatly. In this paper, dynamic analysis using the implicit method in the Finite Element Analysis (FEA) is carried out to assess the factors effecting on flip chips considering underfill. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard is modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. Modal analysis is simulated to find out the relation between drop impact and vibration of the board system.

• 조명전기설비학회논문지
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• 제25권2호
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• pp.80-86
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• 2011

This paper presents an integrated variable amplitude high voltage pulse generation circuit with low power and small size for driving industrial piezoelectric printer heads. To solve the problems of large size and power overhead of conventional pulse generators that usually assembled with multiple high-cost discrete ICs on a PCB board, we have designed a new integrated circuit (IC) chip. Since all the functions are integrated on to a single-chip it can achieve low cost and control the high-voltage output pulse with variable amplitudes as well. It can also digitally control the rising and falling times of an output high voltage pulse by using programmable RC time control of the output buffer. The proposed circuit has been designed and simulatedd in a 180[nm] Bipolar-CMOS-DMOS (BCD) technology using HSPICE and Cadence Virtuoso Tools. The proposed single-chip pulse generation circuit is suitable for use in industrial printer heads requiring a variable high voltage driving capability.

• 한국세라믹학회지
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• 제28권9호
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• pp.675-682
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• 1991

Among many problems that need to be solved in the process of preparing multilayer chip LC filters, we studied the control of shrinkage in order to prevent the crack, warpage, and/or delamination which occurs at the interface between the inductance (L part) and the capacitance (C part). Shrinkage was controlled by compositions, powder size, calcining temperature and amount of organic binder. Capacitance sheet was prepared by mixing 65 wt% binder with the composition of 96 wt% TiO2 having an average particle size of 0.5 $\mu\textrm{m}$, 3 wt% CuO. After small amount of MnO2 and SiO2 added, it was calcined at 750$^{\circ}C$ for 2 hr. Inductance sheet was prepared by mixing 60 wt% binder with the composition of 49.5% mol% Fe2O3, 20.5 mol% ZnO, 20 mol% NiO and 10 mol% CuO which was calcined at 775$^{\circ}C$ for 2 hr. These sheets was laminated at 250 kg/$\textrm{cm}^2$, and cofired at 900$^{\circ}C$ for 2 hr to give rise to a multilayer chip LC filter without any warpage.

• 제어로봇시스템학회논문지
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• 제22권7호
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• pp.513-518
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• 2016

The piezoelectric actuating device is known for its large power density and simple structure. It can generate a larger force than a conventional actuator and has also wide bandwidth with fast response in a compact size. To control the piezoelectric actuator, we need an analog signal conditioning circuit as well as digital microcontrollers. Conventional microcontrollers are not equipped with an analog part and need digital-to-analog converters, which makes the system bulky compared with the small size of piezoelectric devices. To overcome these weaknesses, we are developing a single-chip controller that can handle analog and digital signals simultaneously using mixed-signal FPGA technology. This gives more flexibility than traditional fixed-function microcontrollers, and the control speed can be increased greatly due to the parallel processing characteristics of the FPGA. In this paper, we developed a floating-point multiplier, PWM generator, 80-kHz power control loop, and 1-kHz position feedback control loop using a single mixed-signal FPGA. It takes only 50 ns for single floating-point multiplication. The PWM generator gives two outputs to control the charging and discharging of the high-voltage output capacitor. Through experimentation and simulation, it is demonstrated that the designed control loops work properly in a real environment.

• Journal of Welding and Joining
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• 제16권4호
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• pp.92-97
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• 1998

Because of the low melting temperature of solder, each temperature cycle initiates an irrecoverable creep deformation at the solder interconnection which connects the package body with the PCB. The crack starts and propagates from the position where the creep deformation is maximized. This work has tried to compare and analyze the thermal fatigue life of solder interconnection which is affected by the lead material, the size of die pad, chip thickness, and interface delamination of 48-Pin TSOP under the temperature cycle ($0^{\circ}C$~1$25^{\circ}C$). The crack initiation position and thermal fatigue life which are calculated by using FEA method are well matched with the results of experiments. The thermal Fatigue life of copper lead frame is extended around 3.6 times longer than that of alloy 42 lead frame. It is maximized when the chip size is matched with the length of the lead. It tends to be extended as the thickness of chip got thinner. As the interfacial delamination between die pad and EMC is increased, the thermal fatigue life tends to decrease in the beginning of delamination, and increase after the delamination grew after 45% of the length of die pad.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2002년도 춘계학술대회 논문집
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• pp.308-313
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• 2002

In end milling process, the undeformed chip section area and cutting forces vary periodically with phase change of the tool. However, the real undeformed chip section area deviates from the geometrically ideal one owing to cutter runout and tool shape error. In this study, a method of estimating the real undeformed chip section area which reflects cutter runout and tool shape error was presented during down end-milling of Inconel 715 using measure cutting forces. Contrary to the up-end milling the value of radial specific cutting resistance, $K_r$, becomes larger as the helix angle increases from $30^{\circ}$ to $40^{\circ}$ and it shows almost same value at $50^{\circ}$ The value of tangential specific cutting resistance, $K_t$ becomes larger as the helix angle increases same as in up-end milling, the $KK_r$, and $K_t$ values show a tendency to decrease with increase of the modified chip section area and this tendency is distinct with helix angle $40^{\circ}$.

• 전자공학회논문지A
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• 제33A권10호
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• 한국전기전자재료학회논문지
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• 제24권11호
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• pp.876-881
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• 2011

The sintering, defect and grain boundary characteristics of Bi-based ZnO chip varistor (1,608 mm size) have been investigated to know the possibility of lowering a manufacturing price by using 100 % Ag inner-electrode. The samples were prepared by general multilayer chip varistor process and characterized by shrinkage, SEM, current-voltage (I-V), admittance spectroscopy (AS), impedance and modulus spectroscopy (IS & MS) measurement. There are no problems to make a chip varistor with 100% Ag inner-electrode in the sintering temperature range of 850~900$^{\circ}C$ for 1 h in air. A good varistor characteristics ($V_n$= 9.3~15.4 V, a= 23~24, $I_L$= 1.0~1.6 ${\mu}A$) were revealed but formed $Zn_i^{{\cdot}{\cdot}}$(0.209 eV) as dominant defect, and increased the distributional inhomogeneity and the temperature instability in grain boundary barriers.

• 대한의용생체공학회:의공학회지
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• 제36권4호
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• pp.86-94
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• 2015

In order for medical devices to be used outside hospital, they have to be not only of small size but also power consumption has to be kept at low level. This study investigates the feasibility of application of ADS1298 ECG single-chip solution developed by Texas Instruments Inc. for use in development of a new platform for diagnostic resting ECG. To prove the feasibility of commercial products based on the ADS1298 chip, the performance of the ADS1298 chip was measured in terms of input impedance, common mode rejection, frequency response, and input dynamic range using the testing method under the suitability criteria of the IEC 60601-2-25 standard. Result of the this study shows that commercialization of the ECG products based on the ADS1298 ECG single-chip solution that satisfies the international standards would be possible, if the manufactures take the filter characteristics into account in building a new platform for diagnostic resting ECG.

• 한국전자파학회논문지
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• 제13권6호
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• pp.514-520
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• 2002

본 논문에서는 L-band용 이동통신 단말기에 적용 가능한 수신단 MMIC 믹서의 설계 및 제작에 관한 연구를 다룬다. 단일 칩으로 집적하기 적절한 LO 및 RF balun을 능동소자를 이용하여 구성하였으며 각 능동소자의 공정상의 변화를 보상하기 위하여 새롭게 제안된 바이어스 회로를 적용하였다. 믹서의 변환이득은 -14 dB이며 IP3는 약 4 dBm, 포트간 격리도는 25 dB 이상의 값을 가진다. 제안된 새로운 바이어스 회로는 FET와 저항으로 구성되며 공정상의 변화와 온도의 변화 등에 의한 문턱전압의 변화를 보상해 줄 수 있다. 설계된 칩의 사이즈는 1.4 mm$\times$1.4 mm이다.