• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.41-45
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• 2018

As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.4
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• pp.237-240
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• 2016

The improvement of irradiation intensity and irradiation uniformity is essential for large area and high power UVA light source application. In this study, large number of chips bonded by micro soldering technique were driven by low current, and current limiting diodes were configured to supply constant current to parallel circuits consisting of large number of series strings. The dimension of light source module circuit board was $350{\times}90mm^2$ and 16,650 numbers of 385 nm flip chip LEDs were used with a configuration of 90 parallel and 185 series strings. The space between LEDs in parallel and series strings were maintained at 1.9 mm and 1.0 mm distance, respectively. The size of the flip chip was $750{\times}750{\mu}m^2$ were used with contact pads of $260{\times}669{\mu}m^2$ size, and SAC (96.5 Sn/3.0 Ag/0.5 Cu) solder was used for flip chip bonding. The fabricated light source module with 7.5 m A supply current showed temperature rise of $66^{\circ}C$, whereas irradiation was measured to be $300mW/cm^2$. Inaddition, 0.23% variation of the constant current in each series string was demonstrated.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.108-116
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• 2013

The input buffer in Network on Chip (NoC) router plays a key role in on-chip-network performance, which is utilized in flow control and virtual channel. However, increase in area and power due to input buffers as the network size gets larger is becoming severe. To solve this problem, a bufferless deflection routing without input buffer was suggested. Since the bufferless deflection routing shows poor performance at high network load, other approaches which combine the deflection routing with small size side buffers were also proposed. Nonetheless these new methods still show deficiencies caused by frequent path collisions. In this paper, we propose a modified deflection routing technique using a location based priority. In comparison with existing deflection routers, experimental results show improvement by 12% in throughput with only 3% increase in area.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1023-1028
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• 2012

A MMIC (Monolithic Microwave Integrated Circuit) mixer chip using the Schottky diode of an GaAs p-HEMT process has been developed for the I/Q demodulator of non-contact near field microwave probing system. A single balanced mixer type is adopted to achieve simple structure of the I/Q demodulator. A quadrature hybrid coupler and a quarter wavelength transmission line for 180 degree hybrid are realized with lumped elements of MIM capacitor and spiral inductor to reduce the mixer chip size. According to the on-wafer measurement, this MMIC mixer covers RF and LO frequencies of 1650MHz to 2050MHz with flat conversion loss. The MMIC mixer with miniature size of $2.5mm{\times}1.7mm$ demonstrates conversion loss below 12dB for both variations of RF and LO frequencies, LO-to-IF isolation above 43dB and RF-to-IF isolation above 23dB, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.9-16
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• 2005

This paper presents the development of new anisotropic conductive adhesives with enhanced thermal conductivity for the wide use of adhesive flip chip technology with improved reliability under high current density condition. The continuing downscaling of structural profiles and increase in inter-connection density in flip chip packaging using ACAs has given rise to reliability problem under high current density. In detail, as the bump size is reduced, the current density through bump is also increased. This increased current density also causes new failure mechanism such as interface degradation due to inter-metallic compound formation and adhesive swelling due to high current stressing, especially in high current density interconnection, in which high junction temperature enhances such failure mechanism. Therefore, it is necessary for the ACA to become thermal transfer medium to improve the lifetime of ACA flip chip joint under high current stressing condition. We developed thermally conductive ACA of 0.63 W/m$\cdot$K thermal conductivity using the formulation incorporating $5 {\mu}m$ Ni and $0.2{\mu}m$ SiC-filled epoxy-bated binder system to achieve acceptable viscosity, curing property, and other thermo-mechanical properties such as low CTE and high modulus. The current carrying capability of ACA flip chip joints was improved up to 6.7 A by use of thermally conductive ACA compared to conventional ACA. Electrical reliability of thermally conductive ACA flip chip joint under current stressing condition was also improved showing stable electrical conductivity of flip chip joints. The high current carrying capability and improved electrical reliability of thermally conductive ACA flip chip joint under current stressing test is mainly due to the effective heat dissipation by thermally conductive adhesive around Au stud bumps/ACA/PCB pads structure.

• Journal of Biomedical Engineering Research
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• v.31 no.4
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• pp.292-301
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• 2010

To restore visual sensation of blind patients, we have proposed a fully implantable retinal prosthesis comprising an three dimensionally (3D) stacked retinal chip for transforming optical signal to electrical signal, a flexible cable with stimulus electrode array for stimulating retina cells, and coupling coils for power transmission. The 3D stacked retinal chip is consisted of several LSI chips such as photodetector, signal processing circuit, and stimulus current generator. They are vertically stacked and electrically connected using 3D integration technology. Our retinal prosthesis has a small size and lightweight with high resolution, therefore it could increase the patients` quality of life (QOL). For realizing the fully implantable retinal prosthesis, we developed a retinal prosthesis module comprising a retinal prosthesis chip and a flexible cable with stimulus electrode array for generating optimal stimulus current. In this study, we used a 2D retinal chip as a prototype retinal prosthesis chip. We fabricated the polymide-based flexible cable of $20{\mu}m$ thickness where 16 channels Pt stimulus electrode array was formed in the cable. Pt electrode has an impedance of $9.9k{\Omega}$ at 400Hz frequency. The retinal prosthesis chip was mounted on the flexible cable by an epoxy and electrically connected by Au wire. The retinal prosthesis chip was cappted by a silicone to pretect from corrosive environments in an eyeball. Then, the fabricated retinal prosthesis module was implanted into an eyeball of a rabbit. We successfully recorded electrically evoked potential (EEP) elicited from the rabbit brain by the current stimulation supplied from the implanted retinal prosthesis module. EEP amplitude was increased linearly with illumination intensity and irradiation time of incident light. The retinal prosthesis chip was well functioned after implanting into the eyeball of the rabbit.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.19-23
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• 2014

For the application of light-emitting diodes (LEDs) for general illumination, the development of high power LEDs chips became more essential. For these reasons, recently, modified vertical LEDs have been developed to meet various requirements such as better heat dissipation, higher light extraction and less cost of production. In this research, we investigate the effect of Size and Array of N-GaN contact on operation voltage with new structured padless vertical LED. We changed the size and array of N-electrodes and investigated how they affect the operation voltage of LEDs. We simulated the current crowding and expected operation voltage for different N-contact structures with commercial LED simulator. Also, we fabricated the padless vertical LED chips and measured the electrical property. From the simulation, we could know that the larger size and denser array of n-electrodes could make operation voltage decrease. These results are well in accordance with those measured values of real padless vertical LED chips.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.691-693
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• 1998

A parallel processing systolic array reduces execution time of the Back-propagation ANN. But, systolic array must be designed whenever the number of neurons in the ANN differ. To use the systolic array which is aready designed ad a fixed size VLSI chip, partition of the problem size systolic array must be performed. This paper presents a design method of the fixed size systolic array for the Back-propagation algorthm using LSGP and LPGS partion method

• Transactions of the Korean Society of Mechanical Engineers A
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• v.22 no.1
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• pp.1-15
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• 1998

In this paper, thermo-viscoplastic finite element analysis of the effect of tool edge radius on cutting process are performed. The thermo-viscoplastic cutting model is capable of dealing with free chip geometry and chip-tool contact length. The coupling with thermal effects is also considered. Orthogonal cutting experiments are performed for 0.2% carbon steel with tools having 3 different edge radii and the tool forces are measured. The experimental results are discussed in comparison with the results of the FEM analysis. From the study, we confirm that this cutting model can well be applied to the cutting process considered the tool edge radius and that a major causes of the "size effect" is the tool edge radius. With numerical analysis, the effects of the tool edge radius on the stress distributions in workpiece, the temperature distributions in workpiece and tool, and the chip shape are investigated.estigated.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.62-70
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• 1999

This paper introduces a possibility of a low-cost, high-resolution fingerprint sensor chip. The test chip is composed of $64{\times}256$ sensing cells(chip size : $2.7mm{\times}10.8mm$). A new detection circuit of charge sharing is proposed, which eliminates the influences of internal parasitic copacitances. This the reduced sensing-capacitor size enables a high resolution of 600dpi, using even conventional 0.6${\mu}m$ CMOS process. The partial fingerprint image captured therefrom are synthesized into a full fingerprint image with a image synthesis algorithm. The problems and possibilities of image synthesis technique are also analyzed and discussed.