• 제목/요약/키워드: Chip size

검색결과 1,064건 처리시간 0.025초

GaAs MESFET을 이용한 DSRC용 5.8GHz 대역 ASK-PA One Chip 설계 (Design of an 5.8GHz band ASK-PA one-chip operating for DSRC using a GaAs MESFET)

  • 김병국;하영철;문태정;황성범;김용규;송정근;홍창희
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.755-758
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    • 2003
  • 본 논문에서 단거리전용통신(DSRC)용 OBE에 사용되는 5.8GHz 송신측 ASK와 PA를 one-chip화하여 MMIC로 설계를 및 제작하였다. 설계된 ASK-PA는 3V 단일 공급전원을 사용하였고, 능동 소자로서 GaAs MESFET을 사용하였다. ASK는 회로의 복잡도를 줄이기 위해 직접변조 방식을 채택하였고, 인접채널 간섭의 영향을 줄이기 위하여 드레인 제어 변조회로를 사용하였다. 또한 전력증폭기는 2단으로 하여 AB급으로 동작하도록 전압분배 바이어스회로로 구성하였다. 측정결과 3V의 공급전압에서 전체이득 20.63dB, 송신출력 7.8dBm으로 나타냈다. 공정은 ETRI 0.5㎛ GaAs MESFET 공정을 사용하였고, Chip size는 1.2mm×l.4mm이다.

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효율적인 실시간 영상처리용 2-D 컨볼루션 필터 칩 (An Efficient 2-D Conveolver Chip for Real-Time Image Processing)

  • 은세영;선우명
    • 전자공학회논문지C
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    • 제34C권10호
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    • pp.1-7
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    • 1997
  • This paper proposes a new real-time 2-D convolver filter architecture wihtout using any multiplier. To meet the massive amount of computations for real-time image processing, several commercial 2-D convolver chips have many multipliers occupying large VLSI area. Te proposed architecture using only one shift-and-accumulator can reduce the chip size by more than 70% of commercial 2-D convolver filter chips and can meet the real-time image processing srequirement, i.e., the standard of CCIR601. In addition, the proposed chip can be used for not only 2-D image processing but also 1-D signal processing and has bood scalability for higher speed applications. We have simulated the architecture by using VHDL models and have performed logic synthesis. We used the samsung SOG cell library (KG60K) and verified completely function and timing simulations. The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, that is, 720*480 pixels per frame and 30 frames per second (10.4 mpixels/second).

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Sn-3.5Ag 솔더를 이용한 페리퍼럴 어레이 플립칩의 열 성능 분석

  • 이택영
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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    • pp.270-277
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    • 2003
  • Thermal performance of flip chip bonding with Sn-3.5Ag solder ball was studied. The temperature distribution was measured with IR(InfraRed) camera of 25 urn resolution. The measurement shows that most of the samples had much higher maximum temperature than average temperature. With central heater and 2.5 (W), the difference between maximum and average temperature is over $80^{\circ}C$. The distribution was influenced by the location of heater, the distance from heater to flip chip bonding, and the passivation opening of solder bumps. To reduce the maximum temperature, the bigger passivation opening, the smaller chip size, and the closer location of heater to flip chip bumps are preferrable.

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무선 LAN MAC 계층 설계 및 구현 (Design and Implementation of MAC Protocol for Wireless LAN)

  • 김용권;기장근;조현묵
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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    • pp.253-256
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    • 2001
  • This paper describes a high speed MAC(Media Access Control) function chip for IEEE 802.11 MAC layer protocol. The MAC chip has control registers and interrupt scheme for interface with CPU and deals with transmission/reception of data as a unit of frame. The developed MAC chip is composed of protocol control block, transmission block, and reception block which supports the BCF function in IEEE 802.11 specification. The test suite which is adopted in order to verify operation of the MAC chip includes various functions, such as RTS-CTS frame exchange procedure, correct IFS(Inter Frame Space)timing, access procedure, random backoff procedure, retransmission procedure, fragmented frame transmission/reception procedure, duplicate reception frame detection, NAV(Network Allocation Vector), reception error processing, broadcast frame transmission/reception procedure, beacon frame transmission/reception procedure, and transmission/reception FIEO operation. By using this technique, it is possible to reduce the load of CPU and firmware size in high speed wireless LAN system.

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목질계 바이오에너지자원의 연료화를 위한 기초연구(I) - 목재칲의 물리적 특성 - (Preliminary Study on the Fuel Processing with Woody Biomass (I) - Physical Properties of Wood Chip -)

  • 황진성;오재헌;김남훈;차두송
    • Journal of Forest and Environmental Science
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    • 제25권1호
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    • pp.75-84
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    • 2009
  • This study was conducted to investigate the physical properties of wood chip for fuel processing with woody biomass. Seven species are selected and processed for testing physical properties by 3-type wood chippers which are commonly used in Korea. Wood chips produced by self-propelled drum chipper and fixed type wood chipper equipped with separator were uniform in size and shape. It was shown that the bulk density of produced wood chips was decreased with increasing the wood chip layer thickness, and oak chips prepared by self-propelled drum chipper and fixed type wood chipper showed the highest bulk density.

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Improved Transmitter Power Efficiency using Cartesian Feedback Loop Chip

  • Chong, Young-Jun;Lee, Il-Kyoo;Oh, Seung-Hyeub
    • Journal of electromagnetic engineering and science
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    • 제2권2호
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    • pp.93-99
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    • 2002
  • The Cartesian loop chip which is one of key devices in narrow-band Walky-Talky transmitter using RZ-SSB modulation method was designed and implemented with 0.35 Um CMOS technology. The reduced size and low cost of transmitter were available by the use of direct-conversion and Cartesian loop chip, which improved the power efficiency and linearity of transmitting path. In addition, low power operation was possible through CMOS technology. The performance test results of transmitter showed -23 dBc improvement of IMD level and -30 dEc below suppression of SSB characteristic in the operation of Cartesian loop chip (closed-loop). At that time, the transmitting power was about 37 dBm (5 W). The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

LED 구동 IC를 위한 레벨 시프터 방식의 전하펌프 회로 설계 (Design of a Charge Pump Circuit Using Level Shifter for LED Driver IC)

  • 박원경;박용수;송한정
    • 한국전기전자재료학회논문지
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    • 제26권1호
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    • pp.13-17
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    • 2013
  • In this paper, we designed a charge pump circuit using level shifter for LED driver IC. The designed circuit makes the 15 V output voltage from the 5 V input in condition of 50 kHz switching frequency. The prototype chip which include the proposed charge pump circuit and its several internal sub-blocks such as oscillator, level shifter was fabricated using a 0.35 um 20 V BCD process technology. The size of the fabricated prototype chip is 2,350 um ${\times}$ 2,350 um. We examined performances of the fabricated chip and compared its measured results with SPICE simulation data.

감쇠극을 갖는 적층형 세라믹 칩 필터의 설계 (Design of Multilayer Ceramic Chip Band Pass Filter with an Attenuation Pole)

  • 강종윤;심성훈;최지원;박용욱;이동윤;윤석진;김현재
    • 한국전기전자재료학회논문지
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    • 제16권8호
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    • pp.740-743
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    • 2003
  • A multi-layer ceramic (MLC) chip type band-pass filter (BPF) is presented. The MLC chip BPF has the benefits of low cost and small size. The BPF consists of coulped stripline resonators and coupling capacitors. The BPF is designed to have an attenuation pole at below the passband for a receiver band of IMT-2000 handset. The computer-aided design technology is applied for analysis of the BPF frequency characteristics. The passband and attenuation pole depend on the coupling between resonators and coupling capacitance. The frequency characterics of the passband and attenuation pole are analyzed with the variation of the coupling between resonators and coupling capacitance. An equivanlent circuit and structure of MLC chip BPF are proposed. The frequency characteristics of the BPF is well acceptable for IMT-2000 application.

CSP + HDI : MCM!

  • Bauer, Charles-E.
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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    • pp.35-40
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    • 2000
  • MCM technology languished troughout most of the 1990's due to high costs resulting from low yields and issues with known god die. During the last five years of the decade new developments in chip scale packages and high density, build up multi-layer printed wiring boards created new opportunities to design and produce ultra miniaturized modules using conventional surface mount manufacturing capabilities. Focus on the miniaturization of substrate based packages such as ball grid arrays (BGAs) resulted in chip scale packages (CSPs) offering many of the benefits of flip chip along with the handling, testing, manufacturing and reliability capabilities of packaged deviced. New developments in the PWB industry sought to reduce the size, weight, thickness and cost of high density interconnect (HDI) substrates. Shrinking geometries of vias and new constructions significantly increased the interconnect density available for MCM-L applications. This paper describes the most promising CSP and HDI technologies for portable products, high performance computing and dense multi-chip modules.

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목질세편 세공구조에 따른 음식물쓰레기의 발효·소멸효율 평가 (Evaluation of Fermentation Extinction Rate of Food Waste according to the Various Types of Wood Chip with Different Pore Structures)

  • 오정익;김효진
    • 토지주택연구
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    • 제3권3호
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    • pp.299-305
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    • 2012
  • 음식물쓰레기 발효 소멸용 목질바이오칩의 종류별로 세공구조에 따른 음식물쓰레기 무게 감량율 및 미생물 활동성을 비교분석 하였다. 목질바이오칩을 이용한 음식물쓰레기 발효 소멸실험을 온도 $30{\sim}50^{\circ}C$, 습도 30~70% 조건의 발효 소멸 반응조에 15일간 매일 700~1,500g의 음식물쓰레기를 투입하며 실시하였다. 이 때 1,500g의 목질바이오칩을 발효 소멸 반응조에 초기에 투입하였다. 실험에 사용한 목질바이오칩의 세공구조는 미생물 혼합형(A 바이오칩), $2{\mu}m$ 마크로 세공형(B biochip), $0.1{\mu}m$ 미세공형(C 바이오칩), 점성구조형(D 바이오칩)으로 4가지 유형이었다. 실험결과, A, B, C, D 바이오칩별 발효 소멸에 의한 음식물쓰레기 무게감량율은 각각 85%, 63%, 92%, 73%이었고, C 바이오칩의 경우가 음식물쓰레기 감량율 92%로 최고값을 나타내었다. 또한, C 바이오칩은 ATP/COD $3.00{\times}10^{-10}$, ATP/TN $2.31{\times}10^{-11}$로 상대적으로 타 종류의 바이오칩보다 높은 결과를 나타내었다. 이는 발효 소멸반응에서 발생되는 미생물의 서식지를 충분히 제공하여 ATP/COD 및 ATP/TN이 높아졌고 미생물의 활동성이 강화되어 발효 소멸반응이 원활하게 진행된 결과에 기인하는 것으로 분석되었다.