• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.125-128
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• 2006

This paper presents a novel type soft switching PWM power frequency AC-AC converter using bidirectional active switches or single phase utility frequency AC-high frequency AC matrix converter. This converter can directly convert utility frequency AC (UFAC, 50Hz/60Hz) power to high frequency AC (HFAC) power ranging more than 20kHz up to 100kHz. A novel soft switching PWM prototype of high frequency multi-resonant PWM controlled UFAC-HFAC matrix converter using antiparallel one-chip reverse blocking IGBTs manufactured by IXYS corp. is based on the soft switching resonance with asymmetrical duty cycle PWM strategy. This single phase UFAC-HFAC matrix converter has some remarkable features as electrolytic capacitor DC busline linkless topology, unity power factor correction and sine-wave line current shaping, simple configuration with minimum circuit components, high efficiency and downsizing. This series load resonant UFAC-HFAC matrix converter, incorporating bidirectional active power switches is developed and implemented for high efficiency consumer induction heated food cooking appliances in home uses and business-uses. Its operating performances as soft switching operating ranges and high frequency effective power regulation characteristics are illustrated and discussed on the basis of simulation and experimental results.

• Tribology and Lubricants
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• v.21 no.2
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• pp.71-76
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• 2005

This paper compares of mechanical tensile properties of 6 kinds of copper foil. The beam lead made with copper foil. Different from other package type such as plastic package, Chip Size Package has a reliability problem in beam lead rather than solder joint in board level. A new tensile loading system was developed using voice-coil actuator. The new tensile loading system has a load cell with maximum capacity of 20 N and a non-contact position measuring system based on the principle of capacitance micrometry with 0.1nm resolution for displacement measurement. Strain was calculated from the measured displacement using FE analysis. The comparison of mechanical properties helps designer of package to choose copper for ensuring reliability of beam lead in early stage of semiconductor development.

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.963-966
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• 2015

This paper introduces a programmable multi-format video decoder(MFD) to support HEVC(High Efficiency Video Coding) standard and for other video coding standards. The goal of the proposed MFD is the high-end FHD(Full High Definition) video decoder needed for a DTV(Digital Tele-Vision) SoC(System on Chip). The proposed platform consists of a hybrid architecture that is comprised of reconfigurable processors and flexible hardware accelerators to support the massive computational load and various kinds of video coding standards. The experimental results show that the proposed architecture is operating at a 300MHz clock that is capable of decoding HEVC bit-stream of FHD 30 frames per second.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.318-330
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• 2013

This paper presents a high-linearity low-noise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion differential amplifier and a proposed reconfiguration technique. The proposed differential amplifier combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in $0.18-{\mu}m$ CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from -11 dB to 10 dB with a gain error of less than ${\pm}0.33$ dB, an IIP3 of 7.4~14.5 dBm, a P1dB of -7~1.2 dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270MHz at the maximum gain, respectively. The PGA occupies a chip area of $0.04mm^2$ and consumes only 1.3 mA from the 1.8 V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.697-705
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• 2014

A single chip Programmable AC to DC Power Converter, consisting of wide band gap SiC MOSFET and SiC diodes, has been proposed which converts high frequency ac voltage to a conditioned dc output voltage at user defined given power level. The converter has high conversion efficiency because of negligible reverse recovery current in SiC diode and SiC MOSFET. High frequency operation reduces the need of bigger size inductor. Lead inductors are enough to maintain current continuity. A complete electrical analysis, die area estimation and thermal analysis of the converter has been presented. It has been found that settling time and peak overshoot voltage across the device has reduced significantly when SiC devices are used with respect to Si devices. Reduction in peak overshoot also increases the converter efficiency. The total package substrate dimension of the converter circuit is only $5mm{\times}5mm$. Thermal analysis performed in the paper shows that these devices would be very useful for use as miniaturized power converters for load currents of up to 5-7 amp, keeping the package thermal conductivity limitation in mind. The converter is ideal for voltage requirements for sub-5 V level power supplies for high temperatures and space electronics systems.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.6
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• pp.375-382
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• 2022

This paper proposes a multi-core cooperative computing structure considering the heterogeneous features of automotive embedded on-chip software. The automotive embedded software has the heterogeneous execution flow properties for various hardware drives. Software developed with a homogeneous execution flow without considering these properties will incur inefficient overhead due to core latency and load. The proposed method was evaluated on an target board on which a automotive MCU (micro-controller unit) with built-in multi-cores was mounted. We demonstrate an overhead reduction when software including common embedded system tasks, such as ADC sampling, DSP operations, and communication interfaces, are implemented in a heterogeneous execution flow. When we used the proposed method, embedded software was able to take advantage of idle states that occur between heterogeneous tasks to make efficient use of the resources on the board. As a result of the experiments, the power consumption of the board decreased by 42.11% compared to the baseline. Furthermore, the time required to process the same amount of sampling data was reduced by 27.09%. Experimental results validate the efficiency of the proposed multi-core cooperative heterogeneous embedded software execution technique.

• ETRI Journal
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• v.45 no.1
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• pp.163-170
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• 2023

We report an electroabsorption modulator (EAM)-integrated distributed Bragg reflector laser diode (DBR-LD) capable of supporting a high data rate and a wide wavelength tuning. The DBR-LD contains two tuning elements, plasma and heater tunings, both of which are implemented in the DBR section, which have blue-shift and red-shift in the Bragg wavelength through a current injection, respectively. The light created from the DBR-LD is intensity-modulated through the EAM voltage, which is integrated monolithically with the DBRLD using a butt-joint coupling method. The fabricated chip shows a threshold current of approximately 8 mA, tuning range of greater than 30 nm, and static extinction ratio of higher than 20 dB while maintaining a side mode suppression ratio of greater than 40 dB under a window of 1550 nm. To evaluate its modulation properties, the chip was bonded onto a mount including a radiofrequency line and a load resistor showing clear eye openings at data rates of 25 Gb/s nonreturn-to-zero and 50 Gb/s pulse amplitude modulation 4-level, respectively.

• International Journal of Highway Engineering
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• v.17 no.2
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• pp.89-98
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• 2015

PURPOSES : The objective of this study is to evaluate the performance properties of chip seals and fog seals with polymer-modified emulsions. METHODS : The performance of chip seals and fog seals was evaluated on the basis of common issues in surface treatments. Granite aggregate and four types of asphalt emulsions (one of the unmodified and three of the modified emulsions) were used considering the usage in field. A Vialit test was performed to determine the aggregate retention, and the MMLS3 (Third Scale Model Mobile Load Simulator) test was conducted to determine the aggregate retention, bleeding, and rutting. In addition, the fog seal specimens were tested by the BPT (British Pendulum Test) to evaluate skid resistance. RESULTS AND CONCLUSIONS : Overall, the polymer-modified emulsions (PMEs) showed better aggregate retention and bleeding resistance for both chip seals and fog seals. When comparing the performance of the PMEs, the difference was not considerable. In addition, PMEs present significantly better rutting resistance than unmodified emulsions. For skid resistance, if the recommended mix design is applied, the specimens do not cause issues with skid resistance. Although all of the fog seal specimens were over the criteria for skid resistance, the specimen fabricated by the high emulsion application rate (EAR) of the unmodified emulsion was nearly equivalent to the skid value criteria. Therefore, the use of an unmodified emulsion with a high EAR should be carefully applied in the field.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.16-24
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• 2009

In this paper, DC-DC buck converter with on-chip filter inductor and capacitor is presented. By operating at high switching frequency of 50MHz with stacked interleaved topology, we reduced inductor and capacitor sizes compared to previously published DC-DC buck converters. The proposed circuit is designed in a standard $0.5{\mu}m$ CMOS process, and chip area is $9mm^2$. This circuit operated at the input voltage of $3{\sim}5V$ range, the maximum load current of 250mA, and the maximum efficiency of 71%.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.9
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• pp.6247-6253
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• 2015

This paper presents the transient-response improved LDO regulator based on parallel error amplifiers. The proposed LDO regulator consists of an error amplifier (E/A1) which has a high gain and narrow bandwidth and a second amplifier (E/A2) which has low gain and wide bandwidth. These amplifiers are in parallel structure. Also, to improve the transient-response properties and slew-rate, some circuit block is added. Using pole-splitting technique, an external capacitor is reduced in a small on-chip size which is suitable for mobile devices. The proposed LDO has been designed and simulated using a Megna/Hynix $0.18{\mu}m$ CMOS parameters. Chip layout size is $500{\mu}m{\times}150{\mu}m$. Simulation results show 2.5 V output voltage and 100 mA load current in an input condition of 2.7 V ~ 3.3 V. Regulation Characteristic presents voltage variation of 26.1 mV and settling time of 510 ns from 100mA to 0 mA. Also, the proposed circuit has been shown voltage variation of 42.8 mV and settling time of 408 ns from 0 mA to 100 mA.