• Journal of the Korean Society of Manufacturing Process Engineers
• /
• v.1 no.1
• /
• pp.109-116
• /
• 2002

Resently, reduction of industrial products in size and weight has increased by the application of micro-drill for gadgets of high precision and gave rise to a great interest in a micro-drilling. Due to the lack of tool stiffness and the chip packing, micro-drilling requires not only the robust tool structure which has not affected by the vibration, but also the effective drilling methods designed to prevent tool fracture from cutting troubles. Firstly, this paper presents a new manufacturing process of micro-drill for improving the product rate and an optimum shape of micro-drill for lengthening the tool life, and secondly suggests between tool life and drilling torque acquired in the inprocess monitoring system.

• Transactions of the Korean Society of Machine Tool Engineers
• /
• v.13 no.3
• /
• pp.133-140
• /
• 2004

Recently reduction of industrial products in size and weight has been increased by application of micro-drills in gadgets of high precision and a great interest of a micro-drilling has been raised. Due to the lack of tool stiffness and the chip packing, the micro-drilling requires not only the robust tool structure which has not affected by vibration but also effective drilling methods designed to prevent tool fracture from cutting troubles. This paper presents an optimum design shape of a 0.15 mm micro-drill associated with a new manufacturing process to improve the production rate and to lengthen the tool life and suggestions on the micro-drilling characteristic properties associated with the tool life and workpiece quality.

• Proceedings of the KIEE Conference
• /
• 1991.07a
• /
• pp.857-860
• /
• 1991

This paper describes a High-Speed 8-bit Current-Mode BiCMOS A/D Converter. The characteristics of this A/D Converter are as fellows. First, as ADC is operating in current-mode we can obtain the properties of increase of converting speed, low noise, and wideband. Second, the properties of high switching speed in bipolar transistor and of high packing density, low power consumption in MOS trnsistor are combined. Finally we reduce chip area by designing it with subranging mode and improve the converting speed by performing subtraction directly, which doesn't need D/A convertings, using current switching element. This converter is composed of two 4-bit ADC, current soure array which provides signal and reference current, current comparator and encoding network.

• Transactions of Materials Processing
• /
• v.15 no.9 s.90
• /
• pp.692-696
• /
• 2006

Micro fabrication of polymeric materials becomes increasingly important. And it is considered as a low-cost alternative to the silicon or glass-based Micro Electro-Mechanical System(MEMS) technologies. In the present study, micro channels were fabricated via LiGA(Lithographie, Galvanoformung, Abformung) process used for Capillary Electrophoresis(CE) chip. Taguchi method was applied to investigate the effects of process conditions in injection molding(melt temperature, injection speed, mold temperature and packing pressure) on the transcription characteristics of the micro channel. It was found that the skin layer disturbs a formation of micro channel. Furthermore, mold temperature and injection speed were two important factors to affect the replication characteristics of micro channel.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
• /
• 2001.04a
• /
• pp.287-293
• /
• 2001

Resently, reduction of industrial products in size and weight has increased by the application of micro-drill for gadgets of high precision and gave rise to a great interest in a micro-drilling. Due to the lack of tool stiffness and the chip Packing, micro-drilling requires not only the robust tool structure which has not affected by the vibration, but also the effective drilling methods designed to prevent tool fracture from cutting troubles. Firstly, this paper presents a new manufacturing process of micro-drill for improving the Product rate and an optimum shape of micro-drill for lengthening the tool life, and secondly between tool life and drilling torque acquired in the inprocess monitoring system.

• Transactions of the Korean Society of Machine Tool Engineers
• /
• v.11 no.6
• /
• pp.52-59
• /
• 2002

Resently, reduction of industrial products in size and weight has increased by the application of micro-drill for gadgets of high precision and gave rise to a great interest in a micro-drilling. Due to the lack of tool stiffness and the chip packing, micro-drilling requires not only the robust tool structure which has not affected by the vibration, but also the effective drilling methods designed to prevent tool fracture from cutting troubles. Firstly, this paper presents a optimum characteristic evaluation method of 0.15mm microdrill in consideration of new manufacturing processes for improving the product rate and extend the tool life, and secondly suggest between microdrilling characteristic properties of tool md evaluation of workpiece quality through experiment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.11a
• /
• pp.173-176
• /
• 1999

Continuing improvement of microprocessor performance involves in the devece size. This allow greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However this has led to propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance(RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. Becase of pattering MSSQ (Methylsilsequioxane), we use RIE(Reactive ton Etching) which is a good anisotrgpy. In this study, according as we control a flow rate of CF$_4$/O$_2$ gas, RF power, we analysis by using ${\alpha}$ -step, SEM and AFM,

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.10
• /
• pp.96-106
• /
• 2014

Previous academic research on FPGA tools has relied on simple imaginary models for the targeting architecture. As the first step to overcome such restriction, the issues on analytic placement and legalization which are applied to commercial FPGAs have been brought up, and several techniques to remedy them are presented, and evaluated. First of all, the center of gravity of the placed cells may be far displaced from the center of the chip during analytic placement. A function is proposed to be added to the objective function for minimizing this displacement. And then, the density map is expanded into multiple layers to accurately calculate the density distribution for each of the cell types. Early fixation is also proposed for the memory blocks which can be placed at limited sites in small numbers. Since two flip-flops share control pins in a slice, a compatibility constraint is introduced during legalization. Pre-packing compatible flip-flops is proposed as a proactive step. The proposed techniques are implemented on the K-FPGA fabric evaluation framework in which commercial architectures can be precisely modeled, and modified for enhancement, and validated on twelve industrial strength examples. The placement results show that the proposed techniques have reduced the wire length by 22%, and the slice usage by 5% on average. This research is expected to be a development basis of the optimization CAD tools for new as well as the state-of-the-art FPGA architectures.

• Composites Research
• /
• v.34 no.1
• /
• pp.70-75
• /
• 2021

This paper presents a novel algorithm to reconstruct meso-scale representative volume elements (RVE), referring to experimentally observed features of Sheet Molding Compound (SMC) composites. Predicting anisotropic mechanical properties of SMC composites is challenging in the multiscale virtual test using finite element (FE) models. To this end, an SMC RVE modeler consisting of a series of image processing techniques, the novel reconstruction algorithm, and a FE mesh generator for the SMC composites are developed. First, micro-CT image processing is conducted to estimate probabilistic distributions of two critical features, such as fiber chip orientation and distribution that are highly related to mechanical performance. Second, a reconstruction algorithm for 3D fiber chip packing is developed in consideration of the overlapping effect between fiber chips. Third, the macro-scale behavior of the SMC is predicted by the multiscale analysis.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.3
• /
• pp.28-39
• /
• 1994

We experimented on memory multichip modules to increase the packing density of memory devices and to improve their electrical characteristics. A 128K$\times$8bit SRAM module was made of four 32K$\times$8bit SRAM memory chips. The memory multichip module was constructed on a low-cost double sided PCB(printed circuit boared) substrate. In the process of fabricating a multichip module. we focused on the improvement of its electrical characteristics. volume, and weight by employing bare memory chips. The characteristics of the bare chip module was compared with that of the module with four packaged chips. We conducted circuit routing with a PCAD program, and found the followings: the routed area for the module with bare memory chips reduced to a quarter of that area for module with packaged memory chips. 1/8 in volume, 1/5 in weight. Signal transmission delay times calculated by using transmission line model was reduced from 0.8 nsec to 0.4 nsec only on the module board, but the coupling coefficinet was not changed. Thus, we realized that the electrical characteristics of multichip packages on PCB board be improved greatly when using bare memory chips.