• 대한전자공학회논문지SD
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• 제43권1호
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• pp.71-78
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• 2006

NoC 테스트는 온칩네트워크를 TAM으로 재사용하기 때문에 SoC 구조 기반의 여러 테스트 기법을 그대로 사용할 수가 없다. 본 논문에서는 네트워크 기반 TAM의 문제점을 크게 감소시킨 새로운 형태의 NoC 테스트 플랫폼을 소개하며 이를 이용한 NoC 테스트 스케줄링 알고리즘을 제안한다. 제안한 알고리즘은 SoC 테스트 용도로 개발된 rectangle packing 방식을 기반으로 효율적이고 체계적인 테스트 스케줄링이 가능하게 한다. ITC'02 벤치회로를 이용한 실험 결과 제안한 방법이 기존 방법에 비해 최대 $55\%$까지 테스트 시간을 줄일 수 있음을 확인하였다.

• 한국미생물·생명공학회지
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• 제14권2호
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• pp.199-203
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• 1986

Wood chip을 support로 충전한 관형발효조에 Saccharomyces formosensis 효모용액을 통과시켜 고정화한 관형발효조에서 연속 발효실험을 수행한 결과 wood chip은 support로서 높은 효모 고정화율을 나타내었다. 관형발효조에서 발효실험시 유량 및 농도의 변화시 정상상태에 도달하는데 약 60시간 소요되었고, 정상상태에서 ethanol수율은 0.473-0.483로서 회분식 발효조 경우보다 높은 값을 나타냈다. 정상상태에서 ethanol생산성 (공간체적 기준)은 ethanol농도 61.4-65.7 g/l 범위에서 24.4-19.1g EtOH/$\ell$.hr를 나타내어 다른 고정화법에 의한 것과 비슷하게 높았다. 관형발효조에서 410시간 연속 발효운전시 오염현상이 없었고 효모생존율은 88-93%로 유지되었다.

• 전자공학회논문지A
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• 제32A권3호
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• pp.89-99
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• 1995

In this paper, we ecamined the effect that MCM-L technique influencess on the design and fabrication of multichip memory modules in increasing the packing desity of memory capacity and maximizing its electrical characteristics. For that purpose, we examined the effective methods of reducing the area of module layout and the wiring length with the variation of chip allocation and the number of wiring layers. We fabricated a 256K${\times}$8bit SRAM module with eight 32K${\times}$8bit SRAM chips. The routing experiment showed that we could optimize the area of module layout and wiring length by placing chips in a row, arranging module I/O pads parallel to chip I/O pads, and equalizing the number of terminal sides of module I/O's to that of chip I/O's. The routing was optimized when we used three wire layers in case of one sided chip mounting or five wire layers in case of double sided chip mounting. The fabricated modules showed 18.9 cm/cm$^{2}$ in wiring density, 65 % in substrate occupancy efficiency, and module substrate and functionally tested to find out the module working perfectly.

• ETRI Journal
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• 제28권4호
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• pp.475-485
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• 2006

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

• 전자공학회논문지A
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• 제31A권2호
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• pp.125-134
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• 1994

This paper proposes a new top-down technology mapping algorithm for minimizing the chip area and the path delay time of lookup table-based field programmable gate array(FPGA). First, we present the decomposition and factoring algorithm using common subexpre ssion which minimizes the number of basic logic blocks and levels instead of the number of literals. Secondly, we propose a cube packing algorithm considering the decomposition of gates which exceed m-input lookup table. Previous approaches perform the cube packing and the gate decomposition independently, and it causes to increase the number of basic logic blocks. Lastly, the efficiency.

• 유체기계공업학회:학술대회논문집
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• 유체기계공업학회 2005년도 연구개발 발표회 논문집
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• pp.89-93
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• 2005

In this work, perfusive particles are used to form a micro column in a microfluidic chip and flow properties of the micro column are investigated. The packing flow velocity and the column/particle size ratio are shown to be important parameters affecting the packing density of the micro column. Experimental results show that the effect of the column/particle size ratio on the flow resistance of the micro column is negligible. This contrasts with previous works on the effect of the column/particle size ratio on the total pressure drop across the column.

• 한국산학기술학회논문지
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• 제14권10호
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• pp.4830-4836
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• 2013

본 연구는 "청대추칩"이라는 신제품의 제품 개발 방향 설정을 목적으로 시행되었다. 이를 위하여 청대추칩의 속성별 소비자 가치추정을 실시하였다. 방법적으로는 선택형 실험(Choice Experiment)을 이용하였으며, 조건부 로짓 모형을 추정하여 각 속성별 지불의사금액을 도출하였다. 그 결과 중소기업 제품은 1,333원/개, 대기업은 1,752원/개, 대학은 1,703원/개, 포장 단위는 350원/개, 원료 등급은 548원/개, HACCP은 1,322원/개, ISO22000은 1,166원/개로 추정되었다. 대학 브랜드의 지불의사금액은 중소기업 브랜드보다는 높고 대기업 브랜드보다는 낮은 것으로 나타났다. 대학 브랜드 제품을 다소 고급제품으로 인식하고 있으므로 이에 걸맞는 제품을 개발해야 할 필요가 있다. 그러므로 우선적으로 HACCP을 취득할 필요가 있고 우수한 원료를 사용할 필요가 있다.

• 전자공학회논문지C
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• 제35C권12호
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• pp.31-39
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• 1998

본 논문은 휴대 멀티미디어 응용을 위한 고정 소수점 DSP(Multimedia Fixed-point DSP : MDSP) 칩 설계 및 구현에 관해 기술한다. MDSP는 멀티미디어 처리에 효율적인 명령어 집합을 가지며 SIMD, 벡터프로세싱의 병렬처리 기술과 DSP 기술의 장점을 접목하여 설계되었다. MDSP는 한 개의 데이터 경로가 목적에 따라 여러 개로 분할될 때 8, 16, 32, 40 비트 등의 다양한 데이터 형태의 처리가 가능하며, 멀티미디어 응용영역에서 핵심적인 역할을 하는 MAC 연산을 한 사이클에 2개를 수행하여 성능을 향상시킨다. 새롭게 제안된 스위칭 네트워크와 Packing 네트워크는 MPEG 디코딩, 인코딩, 콘볼루션 등의 알고리즘 처리시 연산과 데이터 변환을 중첩시켜 성능을 향상시킨다. Verilog HDL 모델을 구현하였고 0.6 ㎛ SOG 라이브러리(KG75000)를 이용하여 논리합성 및 시뮬레이션 하였다. 전체 게이트 수는 68,831개이며 MDSP는 30MHz에 동작한다.

• 한국환경보건학회지
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• 제34권1호
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• pp.101-107
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• 2008

Bio-filtration utilizes microorganisms fixed to a porous medium to metabolize pollutants present in an air stream. The microorganisms grow in a bio-film on the surface of a medium or are suspended in the water phase surrounding the medium particles. Therefore, bio-filter support media play one of the most important key roles in bio-filtration of gas phase pollutants. To characterize and select the appropriate support media, gas adsorption capacity and microorganism immobilization were investigated in lab-scale experiments for the selected target support media which were compost I (compost from lab-scale process), compost II (compost from municipal facility), bark, wood chip, orchid stone and vermiculite. As odor materials, ammonia and trimethylamine were utilized. From the result of experiments, bark was superior to any other support media tested in adsorption capacity as much as 12.5 mg ammonia per 1 g bark. In trimethylamine adsorption, bark and wood chip showed a remarkable results of 21.1 and 14.1 mg/g respectively. On the other hand, microorganism fixation test determined by the count of nitrogen oxidizing microbes population, the compost II and wood chips showed the best results. Considering the characteristics of materials and the operating condition of the bio-filter, bark, wood chip, and compost II are applicable to the support media of bio-filter when they are appropriately blended on the basis of studying the media pH, packing porosity and moisture contents.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.264-268
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• 2003

Recently reduction of industrial products in size and weight has been increased by application of micro-drills in gadgets of high precision and a great interest of a micro-drilling has been raised. Due to the lack of tool stiffness and the chip packing, the micro-drilling requires not only the robust tool structure which has not affected by vibration but also effective drilling methods designed to prevent tool fracture from cutting troubles. This paper presents an optimum design shape of a 0.15 mm micro-drill associated with a new manufacturing process to improve the production rate and to lengthen the tool life and suggestions on the micro-drilling characteristic properties associated with the tool life and workpiece quality.