• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.1-9
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• 2010

삼차원 집적화기술의 현황과 과제 및 향후에 요구되어질 새로운 삼차원 집적화기술의 필요성에 대해 논의를 하였다. Super-chip 기술이라 불리우는 자기조직화 웨이퍼집적화 기술 및 삼차원 헤테로집적화 기술에 대해 소개를 하였다. 액체의 표면장력을 이용하여지지 기반위에 다수의 KGD를 일괄 실장하는 새로운 집적화 기술을 적용하여, KGD만으로 구성된 자기조직화 웨이퍼를 다층으로 적층함으로써 크기가 다른 칩들을 적층하는 것에 성공을 하였다. 또한 삼차원 헤테로집적화 기술을 이용하여 CMOS LSI, MEMS 센서들의 전기소자들과 PD, VC-SEL등의 광학소자 및 micro-fluidic 등의 이종소자들을 삼차원으로 집적하여 시스템화하는데 성공하였다. 이러한 기술은 향후 TSV의 실용화 및 궁극의 3-D IC인 super-chip을 구현하는데 필요한 핵심기술이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.255-261
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• 2005

With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 B
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• pp.1055-1057
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• 2001

The switching circuit of PWM inverter is very complicated. By using one-chip $\mu$-com the complication of switching circuit is possible to be diminished. But because in one-chip $\mu$-com the limitation of processed memory size exists, the switching handling method has to be simple. In this paper, to effectively utilize the switching handling, we presented the estimation method of PWM pulses which is different form the conventional PWM switching method by the comparison.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 연구회 합동 학술발표회 논문집
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• pp.5-8
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• 1998

The adaptation to vector control theory is so generalized that it is widely used for implementing the high-performance of AC machine. Nowadays, One-Chip microprocessors or DSP chips are being well-used to implement Vector Control algorithm. DSP Chip have less flexibility for memory decoding and I/O rather than One-Chip microprocessor so that is requires more additional circuit and high cost. And the past One-Chip micro processors have difficult of implementation the complex algorithm because of small memory capacity and low arithmetic performance. Therefore we implemented the vector control algorithm of PMSM(Permanent Magnetic Synchronous Motors) using 80296SA form intel , which have many features as 6M memory space, 500MHz clock frequency, including memory decoding circuit and general I/O, Special I/O(EPA, Interrupt controller, Timer/Count, PWM generator) which is proper controller for the complex algorithm or operation program requiring so much memory capacity, So in this paper we fully digitized the vector control of PMSM included SVPWM Voltage controller using the intel 80296SA

• Natural Product Sciences
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• 제21권3호
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• pp.185-191
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• 2015

Comparative molecular analysis has been frequently adopted for the authentication of herbal medicines as well as the identification of botanical origins. Roots and rhizomes of the family Umbelliferae have been used as traditional herbal medicines to relieve various symptoms such as inflammation, neuralgia and paralysis in countries of East Asia. Since most herbal medicines of the Umbelliferae roots or rhizomes are generally supplied in the form of dried slices, morphological examination does not often provide sufficient evidence to identify the botanical origin. Using species-specific probes developed by the comparative analysis of nrDNA ITS sequences, a DNA chip was developed to identify herbal medicines for 13 species in the Umbelliferae. The developed DNA Chip proves its potential as a rapid, sensitive and effective tool for authenticating herbal medicines in future.

• 전자공학회논문지A
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• 제33A권4호
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• pp.136-141
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• 1996

In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.

• 대한치과의사협회지
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• 제54권5호
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• pp.348-355
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• 2016

Ideal autogenous or allogenic bone graft materials should provide 1) stabilization of blood clot, 2) scaffolds for cellular proliferation and differentiation, 3) release of osteogenic growth factors, 4) appropriate resorption profile for remodeling of new bone. Teeth, especially dentin, mostly contain hydroxyapatite and type I collagen which are similar to bone, and could be valuable graft material. Clinically teeth are used as calcined or demineralized forms. Demineralized form of dentin can be more effective as a graft material. But a conventional decalcification method takes time and long treatment time may give negative effects to various osteogenic proteins in dentin. Author used a new clinical method to prepare autogenous teeth, which could be grafted into the removal defects immediately after extraction using vacuum ultrasonic system. The process could be finished within two hours regardless of the form (powder, chip or block). Teeth were processed to graft materials in block, chip, or powder types immediately after extraction. It took 120 minutes to prepare block types and 40 minutes to prepare powder. Clinical cases did not show any adverse response and the healing was favorable. Rapid preparation of autogenous teeth with the vacuum ultrasonic system could make the immediate one-day extraction and graft possible.

• ETRI Journal
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• 제26권6호
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• pp.560-564
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• 2004

An analog front-end circuit for ISO/IEC 14443-compatible radio frequency identification (RFID) interrogators was designed and fabricated by using a $0.25{\mu}m$ double-poly CMOS process. The fabricated chip was operated using a 3.3 Volt single-voltage supply. The results of this work could be provided as reusable IPs in the form of hard or firm IPs for designing single-chip ISO/IEC 14443-compatible RFID interrogators.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1994년도 FIFTH WESTERN PACIFIC REGIONAL ACOUSTICS CONFERENCE SEOUL KOREA
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• pp.957-962
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• 1994

Real-time RELP vocoder is implemented on the TMS320C25 DSP chip. The implemented system is IBM-PC add-on board and composed of analog in/out unit, DSP unit, memoy unit, IBM-PC interface unit and its supporting assembly software. Speech analyzer and synthesizer is implimented by DSP assembly software. Speech parameters such as LPC coefficients, base-band residuals, and signal gains is extracted by autocorrelation method and inverse filter and synthesized by spectral folding method and direct form synthesis filter in this board. And then, real-time RELP vocoder with 9.6Kbps is simulated by down-loading method in the DSP program RAM.

• 전자공학회논문지A
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• 제29A권9호
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• pp.76-84
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• 1992

The DSP silicon compiler consists of language compiler, module generator, placement tool, router, layout generation tools, and simulator. In this paper, The language compiler, the module generator, placement tool, and simulator were developed and provided for the system designer. The language compiler translates the designer's system description language into the intermediate form file. The intermediate form file expresses the interconnections and specifications of the cells in the cell library. The simulator was developed and provided for the behavioral verification of the DSP system. For its implementation, the event-driven technique and the C$^{++}$ task library was used. The module generator was developed for the layout of the verified DSP system, and generates the functional block to be used in the DSP chip. And then the placement tool determines the appropriate positions of the cells in the DSP chip. In this paper, the placement tool was implemented by Min-Cut and Simulated Annealing algorithm. The placement process can be controlled by the several conditions input by the system designer.