• 대한기계학회논문집
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• 제17권11호
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• pp.2664-2675
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• 1993

In this paper, the effects of chip breaker configuration on cutting forces for various cutting conditions are investigated and a method for predicting cutting forces effectively for chip breaker insert in milling is described. Based on the shear plane model and the relevant equations already existing for the relation among the parameters, the method makes use of the analytic geometric approach considering the configuration of cutting too by a 3-dimensional coordinate transformation matrix. The groove type chip breaker insert is modeled to be a double rake insert, represented by the first radial rake angle, the second radial rake angle and the length of land, and the program analyzing the cutting forces is developed. The program capability is verified by comparing the results with the experimental ones for a single cutter; and in case of primary cutting forces, the results of simulation and experiments agree very well showing 2%~16.7% difference within the feed rate range investigated.

• 조명전기설비학회논문지
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• 제26권6호
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• pp.87-93
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• 2012

In this paper, we propose an analog-to-digital converter to set the address of a I2C slave chip. The proposed scheme converts a fixed voltage between 0 and VDD to the digital value which can be used as the address of the slave chip. The rising time and the falling time are measured with digital counter in a serially connected RC circuit, while the circuit is being charged and discharged with the voltage to be measured. The ratio of the two measured values is used to get the corresponding digital value. This scheme gives a strong point which is to be implementable all the parts except comparator using digital logic. Although the method utilizes RC circuit, it has no relation with the RC value if the quantization error is disregarded. Experimental result shows that the proposed scheme gives 32-level resolution thus it can be used to configure the address of the I2C slave chip.

• Journal of Electrical Engineering and information Science
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• 제2권4호
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• pp.8-13
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• 1997

This paper describes a scalable systolic synchronous memory for digital signal processing and packet switching. The systolic synchronous memory consists of the 2-D array of small memory blocks which are fully pipelined and communicated in three directions with adjacent blocks. The maximum delay of a small memory block becomes the operation speed of the chip. The array configuration is scalable for the entire memory size requested by an application. it has the initial latency of N+3 cycles with NxN array configuration. We designed an experimental 200 MHz 4Kb static RAM chip with the 4x4 array configuration of 256 SRAM blocks. It was fabricated is 0.8$\mu\textrm{m}$ twin-well single-poly double-metal CMOS technology.

• 공업화학
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• 제30권3호
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• pp.379-383
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• 2019

The capability of detecting amyloid beta 42 ($A{\beta}42$), a biomarker of Alzheimer's disease, using a thiolated protein A-functionalized bimetallic surface plasmon resonance (SPR) chip was investigated. An optimized configuration of a bimetallic chip containing gold and silver was obtained through calculations in the intensity measurement mode. The surface of the SPR bimetallic chip was functionalized with thiolated protein A for the immobilization of $A{\beta}42$ antibody. The response of the thiolated protein A-functionalized bimetallic chip to $A{\beta}42$ in the concentration range of 50 to 1,000 pg/mL was linear. Compared to protein A without thiolation, the thiolated protein A resulted in greater sensitivity. Therefore, the thiolated protein A-functionalized bimetallic SPR chip can be used to detect very low concentrations of the biomarker for Alzheimer's disease.

• 전자공학회논문지A
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• 제32A권5호
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• pp.737-748
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• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

• 전기학회논문지P
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• 제58권4호
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• pp.377-384
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• 2009

In this paper, leakage current sensing module of SoC(System on Chip)type and real time monitoring system under consideration of electromagnetic interface in power trunk line are developed. The first, leakage current sensing module of SoC type under consideration of electromagnetic interface is developed, and the developed sensing module of SoC type is composed of leakage sensing part, power supply part, interface part, communication part, AD(Alternating current to Direct current)convert part and amplification part. And also the electromagnetic compatibility is evaluated by conduction and radiation of EMI(Electromagnetic Interference) for developed sensing module. The developed system can have confidence, stability and do energy saving under mixed electric circumstance of the low voltage communication device and high voltage equipment. The second, the real time remote monitoring system is developed using designed wire and wireless communication module with leakage current sensing module of SoC type. The developed real time remote monitoring system can monitor sensing state, occurrence state of leakage current and alarm for each step etc.. And the device configuration, PCB layout for leakage current sensing module of system on chip type and the experiment configuration in consideration of EMI are presented. Also the measurement results of conduction and radiation for EMI are presented.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1993년도 추계학술대회 논문집
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• pp.83-88
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• 1993

Recently, the analysis of microcutting with submicrometer depth of cut is tried to get a more high quality surface product, but to get a valuable result another method instead of conventional finite element method must be considered because finite elment method is impossible for a very small focused region and mesh size. As the altermative method, Molecular Dynamics or Statics is suggested and acceoted in the field of microcutting, indentation and crack propagation. In this paper using Molecuar Dynamics simulation, the phenomena of microcutting with subnanometer chip thickness is studied and the cutting mechanism for tool edge configuration is evaluated. As the result of simulation the atomistic chip formation is achieved.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.368-371
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• 1999

In this paper, we propose a neural network processor architecture with on-chip learning and with reconfigurability according to the data dependencies of the algorithm applied. For the neural network model applied, the proposed architecture can be configured into either SIMD or SRA(Systolic Ring Array) without my changing of on-chip configuration so as to obtain a high throughput. However, changing of system configuration can be controlled by user program. To process activation function, which needs amount of cycles to get its value, we design it by using PWL(Piece-Wise Linear) function approximation method. This unit has only single latency and the processing ability of non-linear function such as sigmoid gaussian function etc. And we verified the processing mechanism with EBP(Error Back-Propagation) model.

• KIEE International Transactions on Electrophysics and Applications
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• 제4C권6호
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• pp.272-275
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• 2004

A balanced single side-band (SSB) mixer employing a sub-harmonic configuration is designed for up and down conversions in K-band. The designed mixer uses anti-parallel diode (APD) pairs to effectively eliminate even harmonics of the local oscillator (LO) spurious signal. To reduce the odd harmonics of LO at the RF port, we employ a balanced configuration for LO. The fabricated chip shows 12$\pm$2dB of conversion loss and image-rejection ratio of about 20dB for down conversion at RF frequencies of 24-27.5GHz. As an up-conversion mode, the designed chip shows 12dB of conversion loss and image-rejection ratio of 20 ～ 25 dB at RF frequencies of 25 to 27GHz. The odd harmonics of the LO are measured below -37dBc.

• 해양환경안전학회지
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• 제20권3호
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• pp.318-322
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• 2014

A kind of field bus called Actuator and Sensor interface bus(AS-i) was designed in this paper. The configuration of AS-i network system used Application Specific Integrated Circuit(ASIC) SAP5S chip and PLC S7-200 station, which included CPU 224 and AS-i master module CP 243-2. We also created an example program for PLC S7-200 to control AS-i network. The fire and smoke detection system was made with AS-i network system that was designed. This system had got more advantages than other system such as number of stations, easy installation, wide working area, etc. And designed system can be used as a partner network for higher level field bus networks.