• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.47-51
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• 2013

Chemical mechanical polishing (CMP) has become one of the key processes in wafer level stacking technology for 3D stacked IC. In this study, two-step CMP process was proposed to polish $Cu/SiO_2$ hybrid bonding surface, that is, Cu CMP was followed by $SiO_2$ CMP to minimize Cu dishing. As a result, Cu dishing was reduced down to $100{\sim}200{\AA}$ after $SiO_2$ CMP and surface roughness was also improved. The bonding interface showed no noticeable dishing or interface line, implying high bonding strength.

• Korean Chemical Engineering Research
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• v.51 no.5
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• pp.622-627
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• 2013

Colloidal silica is used in various industrial products such as chemical mechanical polishing slurry for planarization of silicon and sapphire wafer, organic-inorganic hybrid coatings, binder of investment casting, etc. An accurate determination of particle size and dispersion stability of silica sol is demanded because it has a strong influence on surface of wafer, film of coatings or bulks having mechanical, chemical and optical properties. The study herein is discussed on the effect of measurement results of average particle size, sol viscosity and electrophoretic mobility of particle according to the volume fraction of eight types of silica sol with different size and surface properties of silica particles which are presented by the manufacturer. The measured particle size and the mobility of these sol were changed by volume fraction or particle size due to highly active surface of silica particle and change of concentration of counter ion by dilution of silica sol. While in case the measured sizes of small particles less than 60 nm are increased with increasing volume fraction, the measured sizes of larger particles than 60 nm are slightly decreased. The mobility of small particle such as 12 nm are decreased with increase of viscosity. However, the mobility of 100 nm particles under 0.048 volume fraction are increased with increasing volume fraction and then decreased over higher volume fraction.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1888-1890
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• 1999

In this work, we have systematically studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in Inter-Metal Dielectric(IMD) CMP. The filter Installation in CMP polisher makes defect reduced after IMD CMP. As a result of formation micro-scratches, it shows that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. We have acknowledged slurry filter lifetime is fixed by the degree of generating defects.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.127-132
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• 2012

In this paper, the edge effects of proposed structure in active region for high voltage in shallow trench isolation for very large integrated MOSFET were simulated. Shallow trench isolation (STI) is a key process component in CMOS technologies because it provides electrical isolation between transistors and transistors. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

• Journal of the Korea Society for Simulation
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• v.22 no.4
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• pp.93-98
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• 2013

In this paper, the proposed shallow trench isolation structures for high threshold voltage for very large scale and ultra high voltage integrated circuits MOSFET were simulated. Physically based models of hot-carrier stress and dielectric enhanced field of thermal damage have been incorporated into a TCAD tool with the aim of investigating the electrical degradation in integrated devices over an extended range of stress biases and ambient temperatures. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

• Journal of Korean Society of Water and Wastewater
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• v.18 no.4
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• pp.486-492
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• 2004

CMP (Chemical mechanical polishing) is inevitable process to overcome $0.2{\mu}m$ wire thickness in semiconductor industry. In this study, effect of pressure to separate used CMP slurry into solid and liquid for recycle and reuse by ultrafiltration was investigated. Also, water quality after the ultrafiltration such as turbidity and TDS was evaluated. The material of membrane used in the study was PVDF. The used CMP contained 0.5% of solid content and then concentrated up to 18% by weight. The used CMP can not be concentrated higher than 18% because of viscosity and abrasion of pump. The tested feed pressures were 22.1, 29.4 and 36.8 psi. The results have shown that operating at 36.8 psi has advantages on operation time and total flux. The specific flux showed some variation at 1 to 15 of concentration factor but no difference after 15 of concentration factor. Mass balance of solid at initial stage of the operation showed some unbalance because of deposition of solid on the membrane, which was main reason to reduce flux. Turbidity was very stable at lower than 0.2NTU for 22.1 and 36.8 psi of feed pressure.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2003.10a
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• pp.93-96
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• 2003

Recently, various bulk metallic glasses (BMG's) haying good mechanical and chemical properties were developed. BMG's can easily be deformed in the supercooled liquid region, via viscous flow mechanism. In our previous work, we evaluated the deformation behavior and some other basic properties of Z $r_{41.2}$ $Ti_{13.8}$C $u_{12.5}$N $i_{10}$B $e_{22.5}$ alloy. In this study, we investigated the micro forming of Z $r_{41.2}$ $Ti_{13.8}$C $u_{12.5}$N $i_{10}$B $e_{22.5}$ alloy. The process condition was chosen based on the viscosity data from TMA, and superalloy and Si wafer with micro patterns on the surface were used as forming die. The alloy showed good replication of the patterns. However, some stripe patterns, resembling scratches, appeared on the deformed alloy surface. These scratches can be reduced or eliminated by polishing before forming.ing.ore forming.ing.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.972-975
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• 2002

An understanding of tribological behavior in CMP(Chemical Mechanical Polishing) is one of the most important things to reveal the mechanism of material removal. In CMP, the contact type is thought to be semi-direct, elastohydrodynamic contact type from the Stribeck diagram, which is a combination of solid-solid direct contact and hydrodynamic lubrication with thin liquid film. This study is focused on the decay of friction force during CMP from two points of view, one of which is change of the real contact area and the other is the decrease of the elastic modulus of the pad caused by the increase of the temperature during CMP Experiments are implemented with elastic modulus measuring system and tool dynamometer. Results show that the decay of friction force during CMP results from the decrease of the real contact pressure working on an abrasive, which is induced by the decrease of elastic modulus of pad caused by the increase of temperature. And, the phenomenon is thought to be happen specially in the case that the weight concentration of abrasive in slurry is small enough.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.61-61
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• 2003

CMP(Chemical Mechanical Polishing)는 VLSI의 제조공정에서 실리콘웨이퍼의 절연막내에 있는 토포그래피를 제어할 수 있는 광역 평탄화 기술이다. 또한 최근에는 실리콘웨이퍼의 나노토포그래피(Nanotopography)가 STI의 CMP 공정에서 연마 후 필름의 막 두께 변화에 많은 영향을 미치게 됨으로 중요한 요인으로 대두되고 있다. STI CMP에 사용되는 CeO$_2$ 슬러리에서 첨가되는 계면활성제의 농도에 따라서 나노토포그래피에 미치는 영향을 제어하는 것이 필수적 과제로 등장하고 있다. 본 연구에서는 STI CMP 공정에서 사용되는 CeO$_2$ 슬러리에서 계면활성제의 농도에 따른 나노토포그래피의 의존성에 대해서 연구하였다. 실험은 8 "단면연마 실리콘웨이퍼로 PETEOS 7000$\AA$이 증착 된 것을 사용하였으며, 연마 시간에 따른 나노토포그래피 의존성을 알아보기 위해 연마 깊이는 3000$\AA$으로 일정하게 맞췄다. 그리고 CMP 공정은 Strasbaugh 6EC를 사용하였으며, 패드는 IC1000/SUBA4(Rodel)이다. 그리고 연마시 적용된 압력은 4psi(Pounds per Square Inch), 헤드와 정반(table)의 회전속도는 각각 70rpm이다 슬러리는 A, B 모두 CeO$_2$ 슬러리로 입자크기가 다른 것을 사용하였고, 농도를 달리한 계면활성제가 첨가되었다. CMP 전 후 웨이퍼의 막 두께 측정은 Nanospec 180(Nanometrics)과 spectroscopic ellipsometer (MOSS-ES4G, SOPRA)가 사용되었다.

• Korean Journal of Optics and Photonics
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• v.10 no.5
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• pp.373-378
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• 1999

White light scanning interferometry is increasingly used for precision profile metrology of engineering surfaces, but its current application is primarily limited to opaque surfaces with relatively simple optical reflection behaviors. In this paper, a new attempt is made to extend the interferometric method to the thickness profile measurement of transparent thin film layers. An extensive frequency domain analysis of multiple reflection is performed to allow both the top and bottom interfaces of a thin film layer to be measured independently at the same time using nonlinear least squares technique. This rigorous approach provides not only point-by-point thickness probing but also complete volumetric film profiles digitized in three dimensions.