• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.107-108
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• 2006

In this work, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. $Bi_{3.25}La_{0.75}Ti_{3}O_{12}$ (BLT) ferroelectric film was fabricated by the sol-gel method. However, there have been serious problems in CMP in terms of repeatability and defects in patterned wafer. Especially, dishing & erosion defects increase the resistance because they decrease the interconnect section area, and ultimately reduce the lifetime of the semiconductor. Cross-sections of the wafer before and after CMP were examined by Scanning electron microscope(SEM). Process characteristics of non-dishing and erosion were investigated.

• Journal of Information Display
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• v.3 no.3
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• pp.35-43
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• 2002

Silicon-based 0.69-inch AMOEL microdisplay with integrated driver and timing controller circuits for microdisplay applications has been developed using 0.35 ${\mu}m$ l-poly 4-metal standard CMOS process with 5 V CMOS devices and CMP (Chemical Mechanical Polishing) technology. To reduce the large data programming time consumed in a conventional current programming pixel circuit technique and to achieve uniform display, de-amplifying current mirror pixel circuit and the current-mode data driver circuit with threshold roltage compensation are proposed. The proposed current-mode data driver circuit is inherently immune to the ground-bouncing effect. The Monte-Carlo simulation results show that the proposed current-mode data driver circuit has channel-to-channel non-uniformity of less than ${\pm}$0.6 LSB under ${\pm}$70 mV threshold voltage variaions for both NMOS and PMOS transistors, which gives very good display uniformity.

• Korean Journal of Materials Research
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• v.10 no.11
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• pp.784-788
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• 2000

The Vickers microhardness was measured on the basal (0001) plane of sapphire single crystals in the temperature range from 25$^{\circ}C$to 1000$^{\circ}C$. The substructure surrounding the indents was investigated using selective chemical polishing and etching, optical microscopy, and trasmission electron microscopy (TEM). At room temperature, cracks were predominant, and at intermediate temperatures (400$^{\circ}C$and 600$^{\circ}C$), extensive rhombohedral twinning was observed. On the other hand, at higher temperatures, prism plane slip bands on prism plane {1120}(원문참조) were dominant in the microstructure. TEM observations revealed that the dislocation substructure at the vicinity of the indents consisted of fairly straight dislocations lying in basal and/or prism planes and aligned along the <1100> and <1120> directions. The details of the glide dissociation of perfect <110> screw dislocations into three collinear 1/3<1100> partials on the prism plane and the Peierls potential for sapphire single crystals were discussed.

• KSBB Journal
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• v.21 no.1 s.96
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• pp.1-10
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• 2006

The recovery and purification of a paclitaxel from plant cell cultures is essential to commercial process. This review describes a large-scale recovery and purification method for producing paclitaxel, to guarantee high purity and yield from plant cell cultures. Also, the process of separation and purification is optimized in conjunction with a extraction step, pre-purification, purification, and polishing (drying) as an integrated process to meet final product quality requirements such as purity, residual solvents, product morphologies, impurities, bacterial endotoxin, etc. This information is very useful for production and quality control of pharmaceuticals in commercialization step.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1727-1728
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• 2006

Chemical mechanical polishing (CMP) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, the cost of ownership and cost of consumables are relatively high because of expensive slurry. In this paper, we studied the mixed abrasive slurry(MAS). In order to save the costs of slurry, the original silica slurry was diluted by do-ionized water (DIW). And then, $ZrO_2$,$CeO_2$, and $MnO_2$ abrasives were added in the diluted slurry in order to promote the mechanical force of diluted slurry. We have also investigate the possibility of mixed abrasive slurry for the oxide CMP application.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1357-1358
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• 2006

Indium tin oxide (ITO) thin film is a transparent electrode, which is widely applied to solar battery, illuminators, optical switches, liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting displays (OLEDs) due to its easy formation on glass substrates, goof optical transmittance, and good conductivity. ITO thin film is generally fabricated by various methods such as spray, CVD, evaporation, electron gun deposition, direct current electroplating, high frequency sputtering, and reactive DC sputtering. However, some problems such as peaks, bumps, large particles, and pin-holes on the surface of ITO thin film were reported, which caused the destruction of color quality, the reduction of device life time, and short-circuit. Chemical mechanical polishing (CMP) processis one of the suitable solutions which could solve the problems.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1731-1732
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• 2006

CMP(chemical mechanical polishing) process has been attracted as an essential technology of multi-level interconnection. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, slurry dominates more than 40 %. So, we focused how to reduce the consumption of raw slurry. In this paper, $ZrO_2$, $CeO_2$, and $MnO_2$ abrasives were added de-ionized water (DIW) and pH control as a function of KOH contents. We have investigate the possibility of new abrasive for the oxide CMP application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.93-94
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• 2005

Cu metallization using electrochemical plating(ECP) has played an important role in back end of line(BEOL) interconnect formation. In this work, we studied the optimized copper thickness using Bottom-up Gap-fill in Cu ECP, which is closely related with the pattern dependencies in Cu ECP and Cu dual damascene process at 0.13 ${\mu}m$ technology node. In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge, Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.645-646
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• 2005

The increasing hydroxyl ($OH^-$) groups diffused into the TEOS and then weakened reactants such as H-C-O-Si bonds on the surface of TEOS film were actively generated with the increase of slurry temperature. These soft reactants on the surface of TEOS film could be removed easily by mechanical parts of CMP.