• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.538-538
• /
• 2008

금속계열의 박막을 평탄화하기위해서는 슬러리에 함유된 산화제에 의해 부동태층의 형성이 선행되어야 한다. 따라서 본 논문에서는 Copper 박막의 표면을 부동태층으로 형성시키고 CMP공정을 하기위해 산화제에 dipping을 시켰으며 삼화제의 종류는 $H_2O_2$, MSW2000B, $KIO_3$로 하고 dipping 시간은 30초, 60초, 90초, 3분, 10분으로 하여 시간과 산화제 종류에 따른 부동태층의 변화를 연구하였다. 부동태층의 관찰은 FESEM을 이용하여 표면과 단면을 관찰하였고 부동태층의 조성비율은 EDX를 이용하여 조사하였다. MSW 2000B의 경우는 부동태층이 덩어리 모양으로 형성되었으며 포화현상은 3분에 일어났다. 반면에 $H_2O_2$의 경우는 부동태층이 침상 모양으로 형성되었으며 포화현상은 90초에 일어났다. 산화제에 의해 부동태층을 형성시킨 후 POLI-450을 이용하여 평탄화공정을 진행하였으며 CMP공정조건은 부동태층의 연질상태임을 감안하여 헤드 스피드 20rpm, 플레이튼 스피드 10rpm, 슬러리 주입속도 90ml/min, 공정온도는 상온으로 하여 진행하였다. $H_2O_2$를 산화제로 사용하여 dipping을 하고 CMP를 하였을 경우에 균일한 박막을 확보 할 수 있었으며 CMP 공정 후 copper 박막의 균일성은 FESEM을 이용하여 관찰 하였다.

• Journal of the Korean Society of Industry Convergence
• /
• v.23 no.6_2
• /
• pp.1051-1058
• /
• 2020

The chemical mechanical planarization (CMP) is a process of physically and chemically polishing the semiconductor substrate. The planarization quality of a substrate can be evaluated by the within wafer non-uniformity (WIWNU). In order to improve WIWNU, it is important to manage the pad profile. In this study, a device capable of non-contact measurement of the pad thickness profile was developed. From the measured pad profile, the profile of the pad surface and the groove was extracted using the envelope function, and the pad thickness profile was derived using the difference between each profile. Thickness profiles of various CMP pads were measured using the developed PMS and envelope function. In the case of IC series pads, regardless of the pad wear amount, the envelopes closely follow the pad surface and grooves, making it easy to calculate the pad thickness profile. In the case of the H80 series pad, the pad thickness profile was easy to derive because the pad with a small wear amount did not reveal deep pores on the pad surface. However, the pad with a large wear amount make errors in the lower envelope profile, because there are pores deeper than the grooves. By removing these deep pores through filtering, the pad flatness could be clearly confirmed. Through the developed PMS and the pad thickness profile calculation method using the envelope function, the pad life, the amount of wear and the pad flatness can be easily derived and used for various pad analysis.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.5
• /
• pp.365-371
• /
• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.375-375
• /
• 2010

CdTe as an absorber material is widely used in thin film solar cells with the heterostructure due to its almost ideal band gap energy of 1.45 eV, high photovoltaic conversion efficiency, low cost and stable performance. The deposition methods and preparation conditions for the fabrication of CdTe are very important for the achievement of high solar cell conversion efficiency. There are some rearranged reports about the deposition methods available for the preparation of CdTe thin films such as close spaced sublimation (CSS), physical vapor deposition (PVD), vacuum evaporation, vapor transport deposition (VTD), closed space vapor transport, electrodeposition, screen printing, spray pyrolysis, metalorganic chemical vapor deposition (MOCVD), and RF sputtering. The RF sputtering method for the preparation of CdTe thin films has important advantages in that the thin films can be prepared at low growth temperatures with large-area deposition suitable for mass-production. The authors reported that the optical and electrical properties of CdTe thin film were closely connected by the thickness-uniformity of the film in the previous study [1], which means that the better optical absorbance and the higher carrier concentration could be obtained in the better condition of thickness-uniformity for CdTe thin film. The thickness-uniformity could be controlled and improved by the some process parameters such as vacuum level and RF power in the sputtering process of CdTe thin films. However, there is a limitation to improve the thickness-uniformity only in the preparation process [1]. So it is necessary to introduce the external or additional method for improving the thickness-uniformity of CdTe thin film because the cell size of thin film solar cell will be enlarged. Therefore, the authors firstly applied the chemical mechanical polishing (CMP) process to improving the thickness-uniformity of CdTe thin films with a G&P POLI-450 CMP polisher [2]. CMP process is the most important process in semiconductor manufacturing processes in order to planarize the surface of the wafer even over 300 mm and to form the copper interconnects with damascene process. Some important CMP characteristics for CdTe were obtained including removal rate (RR), WIWNU%, RMS roughness, and peak-to-valley roughness [2]. With these important results, the CMP process for CdTe thin films was performed to improve the thickness-uniformity of the sputtering-deposited CdTe thin film which had the worst two thickness-uniformities of them. Some optical properties including optical transmittance and absorbance of the CdTe thin films were measured by using a UV-Visible spectrophotometer (Varian Techtron, Cary500scan) in the range of 400 - 800 nm. After CMP process, the thickness-uniformities became better than that of the best condition in the previous sputtering process of CdTe thin films. Consequently, the optical properties were directly affected by the thickness-uniformity of CdTe thin film. The absorbance of CdTe thin films was improved although the thickness of CdTe thin film was not changed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.484-484
• /
• 2009

반도체 소자가 차세대 초미세 공정 기술 도입의 가속화를 통해 고속화 및 고집적화 되어 감에 따라 나노 (nano) 크기의 회로 선폭 미세화를 극복하고자 최적의 CMP (chemical mechanical polishing) 공정이 요구되어지고 있다. 최근, 금속배선공정에서 높은 전도율과 재료의 값이 싸다는 이유로 Cu를 사용하였으나, 디바이스의 구조적 특성을 유지하기 위해 높은 압력으로 인한 새로운 다공성 막(low-k)의 파괴와, 디싱과 에로젼 현상으로 인한 문제점이 발생하게 되었다. 이러한 문제점을 해결 하고자 본 논문에서는 Cu의 ECMP 적용을 위해 LSV (Linear sweep voltammetry)법을 통하여 알칼리 성문인 $NaNO_3$ 전해액과 산성성분인 $HNO_3$ 전해액의 전압 활성화에 의한 active, passive, transient, trans-passive 영역을 I-V 특성 곡선을 통해 알아보았고, 알칼리와 산성 성분의 전해액이 Cu 표면에 미치는 영향을 SEM (Scanning electron microscopy), EDS (Energy Dispersive Spectroscopy), XRD(X-ray Diffraction)를 통하여 전기화학적 특성을 비교 분석하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.11b
• /
• pp.171-175
• /
• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectrics and metal, which can apply to employed in integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of free-defects in inter level dielectrics and metal. Especially, defects like (micro-scratch) lead to severe circuit failure, and affects yield. Current conditioning method - bladder type, orbital pad motion- usually provides unsuitable pad profile during ex-situ conditioning near the end of pad life. Since much of the pad wear occurs by the mechanism of bladder type conditioning and its orbital motion without rotation, we need to implement new ex-situ conditioner which can prevent abnormal regional force on pad caused by bladder-type and also need to rotate the pad during conditioning. Another important study of ADPC is related to the orbital scratch of which source is assumed as diamond grit dropped from the strip during ex-situ conditioning. Scratch from diamond grit damaged wafer severely so usually scraped. Figure 1 shows the typical shape of scratch damaged from diamond. e suspected that intensive forces to the edge area of bladder type stripper accelerated the drop of Diamond grit during conditioning. so new designed Flat stripper was introduced.

• Proceedings of the KIEE Conference
• /
• 2006.10a
• /
• pp.105-106
• /
• 2006

The ferroelectric materials of the PZT, SBT attracted much attention for application to ferroelectric random access memory (FRAM) devices. Through the last decade, the lead zirconate titanate (PZT) is one of the most attractive perovskite-type materials for the ferroelectric products due to its higher remanant polarization and the ability to withstand higher coercive fields. FRAM has been currently receiving increasing attention for one of future memory devices due to its ideal memory properties such as non-volatility, high charge storage, and faster switching operations. In this study, we first applied the damascene process using chemical mechanical polishing (CMP) to the fabricate the $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ thin film capacitor in order to solve the problems of plasma etching such as low etching profile and ion charging. The structural characteristics were compared with specimens before and after CMP process of PZT films. The scanning electron microscopy (SEM) analysis was performed to compare the morphology surface characteristics of $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ capacitors. The densification by the vertical sidewall patterning and charging-free ferroelectric capacitor could be obtained by the damascene process without remarkable difference of the characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.42-43
• /
• 2005

본 연구에서는 Cu 슬러리에 부식방지제인 BTA를 첨가하여 슬러리내의 과수의 농도, pH 의 변화, 연마입자의 종류에 따라 연마거동에 미치는 영향과 각 chemical 변화에 따른 Cu surface의 변화를 살펴보았다. BTA (Benzotriazole, $C_6H_4C_3H$)를 첨가함으로써 본 연구에서 시행된 pH 와 과수의 변화에 상관없이 Cu-BTA film을 형성하여 Cu의 dissolution을 최대한 억제하는 것을 확인할 수 있었다. 또 그로인해 BTA를 첨가하지 않았을 때보다 얇은 passivation layer를 형성함을 알 수 있었고 contact angle도 더 높았다. 연마율의 경우에도 BTA가 첨가됨으로써 감소됨을 확인할 수 있었고 연마입자로 alumina particle을 사용한 경우에는 pH6, 과수 10vol%이상에서는 오히려 연마율이 증가하였다. fumed silica의 경우에는 hardness가 작아 mechanical적인 제거력이 낮아 BTA가 첨가되어도 연마율에는 큰 영향이 없었다.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.9
• /
• pp.20-25
• /
• 1998

Cu removal rates for various SiO$_2$ trench pitch sizes and densities and AFM images of surface profiles after global planarization using Cu CMP technology are investigated. In the experimental results, Cu removal rates are increasing as the pattern densities and pattern pitches are getting high and low, respectively, and then decreasing after local planarization. The rms roughness after global planarization are about 120$\AA$. AFM images with a 50% pattern density for 1${\mu}{\textrm}{m}$ and 2${\mu}{\textrm}{m}$ pitches show that thicknesses of 120~330$\AA$ Cu interconnects have been peeled off and oxide erosion of Cu/Sio$_2$ sidewall is observed. However, AFM images with a 50% pattern density for 10${\mu}{\textrm}{m}$ and 15${\mu}{\textrm}{m}$ pitches show that 260~340$\AA$ thick Cu interconnects have been trenched at the boundaries of Cu/Sio$_2$ sidewall.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.05c
• /
• pp.166-169
• /
• 2003

In this study, we evaluated the characteristics by the addition of 3 different kinds of nonionic surfactant to improve the dispersion stability of slurries. Slurry stability is an issue in any industry in which settling of particles can result in poor performance. So we observed the variation of particle size and settling rate when the concentration and addition time of surfactant are changed. When the surfactant is added after milling process, the particle size and pH became low. It is supposed that the particle agglomeration was disturbed by adsorption of surfactant on alumina abrasive. The settling rate was relatively stable when nonionic surfactant is added about 0.1~1.0 wt%. When molecular weight(MW) is too small like Brij 35, it was appeared low effect on dispersion stability. Because it can't prevent coagulation and subsequent settling with too small MW. The proper quality of MW for slurry stability was presented about 500,000. Consequently, the addition of nonionic surfactant to alumina slurry has been shown to have very good effect on slurry stabilization. If we apply this results to copper CMP process, it is thought that we will be able to obtain better yield.