• International Journal of Advanced Culture Technology
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• v.9 no.4
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• pp.392-401
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• 2021

When a data file is shared through various methods on the Internet, the data file may be damaged in various cases. To prevent this, some websites provide the checksum value of the download target file in text data type. The checksum value provided in this way is then compared with the checksum value of the downloaded file and the published checksum value. If they are the same, the file is regarded as the same. However, the checksum value provided in text form is easily tampered with by an attacker. Because of this, if the correct checksum cannot be verified, the reliability and integrity of the data file cannot be ensured. In this paper, a checksum value is generated to ensure the integrity and reliability of a data file, and this value and related file information are stored in the blockchain. After that, we will introduce the research contents for designing and implementing a system that provides a function to share the checksum value stored in the block chain and compare it with other people's files.

• Proceedings of the Korea Information Processing Society Conference
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• 2006.05a
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• pp.1147-1150
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• 2006

Stream Control Transmission Protocol (SCTP) uses the 32-bit checksum in the common header, by which a corrupted SCTP packet will be regarded as a lost packet and then discarded. This may result in degradation of SCTP's throughput performance over wireless networks. This paper proposes a new chunk checksum scheme for SCTP, in which each data chunk contains its own checksum field and SACK chunk carry corresponding Transmission Sequence Number (TSN) with timestamp for every corruption event. The proposed chunk checksum scheme is introduced with the following three purposes: 1) to distinguish the chunk corruptions from the chunk losses; 2) to avoid the unnecessary halving of the congestion window (cwnd) in the case of chunk corruption; 3) to avoid the unwanted timeouts which can be induced in conventional SCTP in the case that the retransmitted data chunks are corrupted again in wireless networks. Simulation results show that the proposed chunk checksum scheme could improve the SCTP throughput in the wireless environments with a high bit error rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6C
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• pp.619-625
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• 2009

This paper proposes a parallel architecture of a Parity Checksum Generator adopted for packet synchronization and error detection in the ITU-T Recommendation J.83 Annex B. The proposed parallel processing architecture removes a performance bottleneck occurred in a conventional serial processing architecture, leading to significant decrease in processing time for generating a Parity Checksum. The implementation results show that the proposed parallel processing architecture reduces the processing time by 83.1% at the expense of 16% area increase.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1029-1032
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• 1998

In this paper, a comparative study is presented to evaluate the addition architecture of the high-speed checksum module in TCP/IP processing. In order to speed up TCP/IP processing, H/W implementation offers concurrent and parallel processing to yield high speed computation, with respect to S/W implementation. This research aims at comparing two addition architectures of checksum module, which is the major botteleneck in TCP/IP processing. The 16-bit and 8-bit byte-by-byte addition architecture are implemented by the full custom design, and compared, in analytical and experimental manner, from standpoint of space and performance. For LG $0.6\mu\textrm{m}$ TLM process, the 8-bit addition implementation requires the area, 1.3 times larger than the 16-bit one, and it operates at 80MHz while the 16-bit one runs by 66MHz.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.927-930
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• 2003

In this paper, a design of processor IP for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability. To handle the various modes of TCP/IP protocol, hardware and software co-design approach is used rather than the conventional state machine based design. To eliminate delay time due to the data transfer and checksum operation, DAM module which can execute the checksum operation on-the-fly along with data transfer operation is adopted. By programming the on-chip code ROM of RISC processor differently. the designed stack processor can support the packet format conversion operations required in the various TCP/IP protocols.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.8 no.1
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• pp.76-81
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• 2009

The transmitting node in WSN for ITS would be small and operated by battery, and the MCU in the node would be low speed with small sized memory and low power consumption. In this paper, the post-checksum method in which the checksum field is added to the tail of the TCP segment for ITS applications, is proposed to reduce data processing time and power consumption, and so there is no limitation of the transmitting data size.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.1977-1983
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• 1998

An algorithm-based fault tolerant scheme for the vector convolution is proposed employing the positive and negative checksum vectors that are defined in this paper based on the encoder vector. The proposed scheme is implemented on the aray processor, and then the amount of redundancy is examined thrugh the complexity analysis.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1166-1174
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• 2004

In this paper, a design of RISC-based transmission wrapper processor for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability, and memory module. To handle the various modes of TCP/IP protocol, hardware-software codesign approach based on RISC processor is used rather than the conventional state machine design. To eliminate large delay time due to sequential executions of data transfer and checksum operation, DMA module which can execute the checksum operation along with data transfer operation is adopted. The designed processor exclusive of variable-size input/output buffer consists of about 23,700 gates and its maximum operating frequency is about 167MHz under 0.35${\mu}m$ CMOS technology.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.639-645
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• 2015

Checksum and residue checking accelerators were implemented on a Nios II core-based platform according to component method, in which the corresponding hardware was implemented with HDL coding, a custom instruction method, in which the instruction set of the processor was extended, and the C2H method, in which the corresponding logic was automatically created by the C2H compiler. The processing results from each accelerator for each algorithm were then examined and compared. The results of the comparison showed that the accelerator implemented with the C2H method is the fastest in terms of the execution time, and the accelerator with custom instruction requires the least add-on from the viewpoint of add-on hardware.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11B
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• pp.736-743
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• 2005

NAT-PT is one of the IPv6 transition mechanisms, as defined in RFC2766, allowing IPv6-only devices to communicate with IPv4-only devices and vice versa. In NAT-PT, sender fail to verify TCP/UDP checksum and authentication data due to IP translation in the NAT-PT server The NAT-PT, therefore, has a limit to applying the IPsec that provides the end-to-end security such as confidentiality, authentication, and integrity. This paper proposes a scheme to apply the IPsec using IP HTI in NAT-PT environment.