• Asia Pacific Journal of Business Review
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• v.4 no.1
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• pp.1-34
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• 2019

This study investigates whether and how a firm's cost of equity capital is influenced by the extent of a firm's real earnings management (REM). Using a large sample of Hong Kong and Chinese firms over the 9-year period 2009-2017, we find that our implied cost of equity estimates are positively associated with both the extent of REM and the extent of accrual-based earnings management (AEM), but the positive association is stronger for REM than for AEM. We also provide evidence suggesting that the effect of AEM and REM on the cost of equity is more pronounced for Hong Kong firms than Chinese firms, and within Chinese firms, it is less pronounced for the state-owned enterprises (SOEs). Collectively, our results suggest that while both REM and AEM exacerbate the quality of earnings used by outside investors, REM does so to a greater extent than AEM, and thus the market demands a higher risk premium for REM activities than for AEM activities and that this cost of capital-increase effect is more prominent in a developed market like Hong Kong and mitigated by state ownership in China because of investors' expectations for a lower level of detriments to firm fundamentals by REM due to government's protection in a less developed market like China.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.2
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• pp.268-275
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• 2020

A lightweight hardware design of self-timed ring based true random number generator (TRNG) suitable for information security applications is described. To reduce hardware complexity of TRNG, an entropy extractor with feedback structure was proposed, which minimizes the number of ring stages. The number of ring stages of the FSTR-TRNG was determined to be a multiple of eleven, taking into account operating clock frequency and entropy extraction circuit, and the ratio of tokens to bubbles was determined to operate in evenly-spaced mode. The hardware operation of FSTR-TRNG was verified by FPGA implementation. A set of statistical randomness tests defined by NIST 800-22 were performed by extracting 20 million bits of binary sequences generated by FSTR-TRNG, and all of the fifteen test items were found to meet the criteria. The FSTR-TRNG occupied 46 slices of Spartan-6 FPGA device, and it was implemented with about 2,500 gate equivalents (GEs) when synthesized in 180 nm CMOS standard cell library.