• Transactions on Electrical and Electronic Materials
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• 제15권5호
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• pp.245-248
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• 2014

$Pt/Al_2O_3/Si_3N_4/SiO_2/Si$ charge trap flash memory structures with various thicknesses of the $Si_3N_4$ charge trapping layer were fabricated. According to the calculated and measured results, we depicted electron loss in a schematic diagram that illustrates how the trap to band tunneling and thermal excitation affects electrons loss behavior with the change of $Si_3N_4$ thickness, temperature and trap energy levels. As a result, we deduce that $Si_3N_4$ thicknesses of more than 6 or less than 4.3 nm give no contribution to improving memory performance.

• 한국전기전자재료학회논문지
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• 제22권1호
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• Transactions on Electrical and Electronic Materials
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• 제17권1호
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• pp.25-28
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• 2016

We investigate the effect of interface states on the endurance of a charge trap flash (CTF) NOR array using charge pumping methods. The endurance test was completed from one cell selected randomly from 128 bit cells, where the memory window value after 10² program/erase (P/E) cycles decreased slightly from 2.2 V to 1.7 V. However, the memory window closure abruptly accelerated after 10³ P/E cycles or more (i.e. 0.97 V or 0.7 V) due to a degraded programming speed. On the other hand, the interface trap density (Nit) gradually increased from 3.13×10¹¹ cm⁻² for the initial state to 4×10¹² cm⁻² for 10² P/E cycles. Over 10³ P/E cycles, the Nit increased dramatically from 5.51×10¹² cm⁻² for 10³ P/E cycles to 5.79×10¹² cm⁻² for 10⁴ P/E cycles due to tunnel oxide damages. These results show good correlation between the interface traps and endurance degradation of CTF devices in actual flash cell arrays.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.34-39
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• 2014

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제37회 하계학술대회 초록집
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• pp.211-211
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• 2009

• 대한전자공학회논문지SD
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• 제45권7호
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• pp.37-43
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• 2008

본 논문에서는 전하 펌프 방법 (Charge Pumping Method, CPM)를 이용하여 서로 다른 질화막 층을 가지는 N-Channel SANOS (Silicon-$Al_2O_3$-Nitride-Oxide-Silicon) Flash Memory Cell 트랜지스터의 트랩 특성을 규명하였다. SANOS Flash Memory에서 계면 및 질화막 트랩의 중요성은 널리 알려져 있지만 소자에 직접 적용 가능하면서 정화하고 용이한 트랩 분석 방법은 미흡하다고 할 수 있다. 기존에 알려진 분석 방법 중 전하 펌프 방법은 측정 및 분석이 간단하면서 트랜지스터에 직접 적용이 가능하여 MOSFET에 널리 사용되어왔으며 최근에는 MONOS/SONOS 구조에도 적용되고 있지만 아직까지는 Silicon 기판과 tunneling oxide와의 계면에 존재하는 트랩 및 tunneling oxide가 얇은 구조에서의 질화막 벌크 트랩 추출 결과만이 보고되어 있다. 이에 본 연구에서는 Trapping Layer (질화막)가 다른 SONOS 트랜지스터에 전하 펌프 방법을 적용하여 Si 기판/Tunneling Oxide 계면 트랩 및 질화막 트랩을 분리하여 평가하였으며 추출된 결과의 정확성 및 유용성을 확인하고자 트랜지스터의 전기적 특성 및 메모리 특성과의 상관 관계를 분석하고 Simulation을 통해 확인하였다. 분석 결과 계면 트랩의 경우 트랩 밀도가 높고 trap의 capture cross section이 큰 소자의 경우 전자이동도, subthreshold slop, leakage current 등의 트랜지스터의 일반적인 특성 열화가 나타났다. 계면 트랩은 특히 Memory 특성 중 Program/Erase (P/E) speed에 영향을 미치는 것으로 나타났는데 이는 계면결함이 많은 소자의 경우 같은 P/E 조건에서 더 많은 전하가 계면결함에 포획됨으로써 trapping layer로의 carrier 이동이 억제되기 때문으로 판단되며 simulation을 통해서도 동일한 결과를 확인하였다. 하지만 data retention의 경우 계면 트랩보다 charge trapping layer인 질화막 트랩 특성에 의해 더 크게 영향을 받는 것으로 나타났다. 이는 P/E cycling 횟수에 따른 data retention 특성 열화 측정 결과에서도 일관되게 확인할 수 있었다.

• Transactions on Electrical and Electronic Materials
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• 제16권3호
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• pp.130-134
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• 2015

This research proposes the use of a composition modulated (ZrO₂)_x(Al₂O₃)_1-x film as a charge trapping layer for charge trap flash memory; this is possible when the Zr (Al) atomic percent is controlled to form a variable bandgap as identified by the valence band offsets and electron energy loss spectrum measurements. Compared to memory devices with uniform compositional (ZrO₂)_0.1(Al₂O₃)_0.9 or a (ZrO₂)_0.92(Al₂O₃)_0.08 trapping layer, the memory device using the composition modulated (ZrO₂)_x(Al₂O₃)_1-x as the charge trapping layer exhibits a larger memory window (6.0 V) at the gate sweeping voltage of ±8 V, improved data retention, and significantly faster program/erase speed. Improvements of the memory characteristics are attributed to the special energy band alignments resulting from non-uniform distribution of elemental composition. These results indicate that the composition modulated (ZrO₂)_x(Al₂O₃)_1-x film is a promising candidate for future nonvolatile memory device applications.

• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.831-837
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• 2002

Scaled SONOS transistors have been fabricated by 0.35$\mu\textrm{m}$ CMOS standard logic process. The thickness of stacked ONO(blocking oxide, memory nitride, tunnel oxide) gate insulators measured by TEM are 2.5 nm, 4.0 nm and 2.4 nm, respectively. The SONOS memories have shown low programming voltages of ${\pm}$8.5 V and long-term retention of 10-year Even after 2 ${\times}$ 10$\^$5/ program/erase cycles, the leakage current of unselected transistor in the erased state was low enough that there was no error in read operation and we could distinguish the programmed state from the erased states precisely The tight distribution of the threshold voltages in the programmed and the erased states could remove complex verifying process caused by over-erase in floating gate flash memory, which is one of the main advantages of the charge-trap type devices. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ cycles can be realized by the programming method for a flash-erased type EEPROM.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.604-607
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• 2008

본 연구에서는 NAND 플래시메모리를 위한 기본 셀로서 p채널 SONOS (silicon-oxide-nitride-oxide-silicon) 트랜지스터를 제작하고 이것의 메모리특성을 조사하였다. SONOS 트랜지스터의 제작은 $0.13{\mu}m$ low power용 standard logic 공정기술을 사용하였다. 게이트 절연막의 두께는 터널 산화막 $20{\AA}$, 질화막 $14{\AA}$, 그리고 블로킹산화막의 두께는 $49{\AA}$이다. 제작된 SONOS 트랜지스터는 낮은 쓰기/지우기 전압, 빠른 지우기 속도, 그리고 비교적 우수한 기억유지특성과 endurance 특성을 나타내었다.