• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.34-39
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• 2014

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.34-34
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• 2009

The electrical characteristics of tunnel barrier engineered charge trap flash (TBE-CTF) memory with $SiO_2/Si_3N_4/SiO_2/Si$ engineered tunnel barrier, $HfO_2$ charge trap layer and $Al_2O_3$ blocking oxide layer (MAHONOS) were investigated. The energy bad diagram was designed by using the quantum-mechanical tunnel model (QM) and then the CTF memory devices were fabricated. As a result, the best thickness combination of MAHONOS is confirmed. Moreover, not enhanced P/E speed (Program: about $10^6$ times) (Erase: about $10^4$ times) but also enhanced retention and endurance characteristics are represented.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

• Transactions on Electrical and Electronic Materials
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• v.15 no.5
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• pp.245-248
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• 2014

$Pt/Al_2O_3/Si_3N_4/SiO_2/Si$ charge trap flash memory structures with various thicknesses of the $Si_3N_4$ charge trapping layer were fabricated. According to the calculated and measured results, we depicted electron loss in a schematic diagram that illustrates how the trap to band tunneling and thermal excitation affects electrons loss behavior with the change of $Si_3N_4$ thickness, temperature and trap energy levels. As a result, we deduce that $Si_3N_4$ thicknesses of more than 6 or less than 4.3 nm give no contribution to improving memory performance.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.211-211
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• 2009

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.200.1-200.1
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• 2015

Charge trap flash (CTF) 메모리 소자는 기존의 플로팅 게이트를 사용한 플래시 메모리 소자에 비해 쓰고 지우는 속도가 빠르고, 소비 전력이 적으며, 쓰고 지우는 동작에 의한 전계 스트레스에 잘 견뎌내는 장점을 가지고 있다. 그러나 CTF 메모리 소자에서도 메모리 셀의 크기가 작아짐에 따라 셀 사이의 간섭 효과를 무시할 수 없다. 인접 셀 간의 간섭현상은 측정 셀의 문턱전압을 예측할 수 없게 변화시켜 소자 동작의 신뢰성을 낮추고 성능을 저하시킨다. 본 논문에서는 셀 사이의 간섭을 줄이고 소자의 성능을 향상시키기 위해 charge trap 층에 금속 공간층을 삽입한 CTF메모리 소자의 전기적인 특성에 대해 연구하였다. 금속 공간층을 갖는 CTF 메모리 소자는 기존 CTF 메모리 소자의 트랩층 양 측면에 절연막과 금속 공간층을 증착시켜 게이트가 트랩층을 감싸는 구조를 갖는다. 인접 셀 사이에 발생하는 간섭 현상과 전계 분포를 분석하였다. 프로그램 동작 시CTF 메모리 소자 내에 형성되는 전계의 분포와 크기를 계산함으로 금속 공간층이 인접한 셀에서 형성된 전계를 차폐시켜 셀 간 간섭 현상을 최소화하는 것을 확인하였다. 이러한 결과는 인접 셀 간의 간섭현상을 최소화하면서 소자 동작의 신뢰성이 향상된 대용량 메모리 소자를 제작하는데 도움을 줄 수 있다.

• Transactions on Electrical and Electronic Materials
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• v.15 no.5
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• pp.241-244
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• 2014

Charge trap flash memory capacitors incorporating $(HfO_2)_x(Al_2O_3)_{1-x}$ film, as the charge trapping layer, were fabricated. The effects of the charge trapping layer composition on the memory characteristics were investigated. It is found that the memory window and charge retention performance can be improved by adding Al atoms into pure $HfO_2$; further, the memory capacitor with a $(HfO_2)_{0.9}(Al_2O_3)_{0.1}$ charge trapping layer exhibits optimized memory characteristics even at high temperatures. The results should be attributed to the large band offsets and minimum trap energy levels. Therefore, the $(HfO_2)_{0.9}(Al_2O_3)_{0.1}$ charge trapping layer may be useful in future nonvolatile flash memory device application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.37-43
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• 2008

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program/erase (P/E) speed, reliability of memory device on interface trap between Si substrate and tunneling oxide and bulk trap in nitride layer were investigated using charge pumping method which has advantage of simple and versatile technique. We analyzed different SANOS memory devices that were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SANOS cell transistors with larger capture cross section and interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. The data retention was deteriorated as increasing P/E cycling number but not coincides with interface trap increasing tendency. This result once again confirmed that interface trap independence on data retention. And the result on different program method shows that HCI program method more degraded by locally trapping. So, we know as a result of experiment that analysis the SANOS Flash memory characteristic using charge pumping method reflect the device performance related to interface and bulk trap.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.104.2-104.2
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• 2009

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.831-837
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• 2002

Scaled SONOS transistors have been fabricated by 0.35$\mu\textrm{m}$ CMOS standard logic process. The thickness of stacked ONO(blocking oxide, memory nitride, tunnel oxide) gate insulators measured by TEM are 2.5 nm, 4.0 nm and 2.4 nm, respectively. The SONOS memories have shown low programming voltages of ${\pm}$8.5 V and long-term retention of 10-year Even after 2 ${\times}$ 10$\^$5/ program/erase cycles, the leakage current of unselected transistor in the erased state was low enough that there was no error in read operation and we could distinguish the programmed state from the erased states precisely The tight distribution of the threshold voltages in the programmed and the erased states could remove complex verifying process caused by over-erase in floating gate flash memory, which is one of the main advantages of the charge-trap type devices. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ cycles can be realized by the programming method for a flash-erased type EEPROM.