• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

• Journal of Power Electronics
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• 제17권3호
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• pp.621-631
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• 2017

A KY converter integrated with a conventional synchronously rectified (SR) boost converter and a coupled inductor is presented in this paper. This improved KY converter has the following advantages: 1) the two converters use common switches; 2) the voltage gain of the KY converter can be improved due to the integration of a boost converter and a coupled inductor; 3) the leakage inductance of the coupled inductor is utilized to achieve zero voltage switching (ZVS); 4) the current stress on the charge pump capacitors and the decreasing rate of the diode current can be limited due to the use of the coupled inductor; and 5) the output current is non-pulsating. Moreover, the active switches are driven by using one half-bridge gate driver. Thus, no isolated driver is needed. Finally, the operating principle and analysis of the proposed converter are given to verify the effectiveness of the proposed converter.

• 대한전자공학회논문지SD
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• 제40권11호
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• pp.45-53
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• 2003

DRAM에서 사용되는 내부 승압 전원 전압과 기판인가 전원 전압 발생기를 공유함으로써 단일 Charge Pump에서 승압 전원과 기판 전원을 동시에 발생시키는 회로를 설계하였다. 이 회로는 0.14um의 DRAM 공정을 사용하여 기존 보다 전력 소모를 30%, 전체 면적을 40% 그리고 Pumping capacitor 면적을 29.6% 각각 감소하였으며 또한 전류 공급 효율을 13.2% 향상 시켰다. Charge Recycling 기법을 적용하여 Pumping capacitor의 Precharge 구간 동안 소모되는 전류를 75% 감소하였다.

• 한국수소및신에너지학회논문집
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• 제26권4호
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• pp.324-330
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• 2015

The electrolyte flow rates of vanadium redox flow battery play very important role in terms of ion transfer to electrolyte, kinetics and pump efficiency in system. In this paper a vanadium redox flow battery single cell was tested to suggest the optimization criteria of electrolyte flow rates on the efficiencies. The compared electrolyte circulation flow rates in this experimental work were 15, 30 and 45 mL/min. The charge/discharge characteristics of the flow rate of 30 mL/min was the best out of all flow rates in terms of charging and discharging time. The current efficiencies, voltage efficiencies and energy efficiencies at the flow rate of 30 mL/min were the best. The IR losses obtained at thd current density of $40mA/cm^2$, at the flow rates of 15, 30 and 45 mL/min were 0.085 V, 0.042 V and 0.115 V, respectively. The charge efficiencies at the current density of $40mA/cm^2$ were 96.42%, 96.45% and 96.29% for the electrolyte flow rates of 15, 30 and 45 mL/min, respectively. The voltge efficiencies at the current density of $40mA/cm^2$ were 77.34%, 80.62% and 76.10% for the electrolyte flow rates of 15, 30 and 45 mL/min, respectively. Finally, the energy efficiencies at the current density of $40mA/cm^2$ were 74.57%, 77.76% and 73.27% for the electrolyte flow rates of 15, 30 and 45 mL/min, respectively. The optimum flow rates of electrolytes were 20 mL/min in most of operating variables of vanadium redox flow battery.

• Journal of Power Electronics
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• 제15권3호
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• pp.587-601
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• 2015

A high step-up dc-dc converter is proposed for photovoltaic power systems in this paper. The proposed converter consists of an input current doubler, a symmetrical switched-capacitor doubler and an active-clamp circuit. The input current doubler minimizes the input current ripple. The symmetrical switched-capacitor doubler is composed of two symmetrical quasi-resonant switched-capacitor circuits, which share the leakage inductance of the transformer as a resonant inductor. The rectifier diodes (switched-capacitor circuit) are turned off at the zero current switching (ZCS) condition, so that the reverse-recovery problem of the diodes is removed. In addition, the symmetrical structure results in an output voltage ripple reduction because the voltage ripples of the charge/pump capacitors cancel each other out. Meanwhile, the voltage stress of the rectifier diodes is clamped at half of the output voltage. In addition, the active-clamp circuit clamps the voltage surges of the switches and recycles the energy of the transformer leakage inductance. Furthermore, pulse-width modulation plus phase angle shift (PPAS) is employed to control the output voltage. The operation principle of the converter is analyzed and experimental results obtained from a 400W prototype are presented to validate the performance of the proposed converter.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.489-492
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• 2000

A novel low-cost simple and unity-power-factor electronic ballast is presented. The proposed electronic ballast employs a bypassing capacitor and load networks composed of ballast capacitors and small charge pump capacitors as power factor correction circuit combined with the secondary winding of the transformer in the self-excited current-fed push-pull resonant inverter(CF-PPRI) resulting in cost-effectiveness and higher efficiency. By analyzing the principles of power factor correction mathematically optimum design guidelines are presented. Since the lamps are used in power factor correction stage the input power is automatically adjusted according to the number of the lamps.

• 마이크로전자및패키징학회지
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• 제8권1호
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• pp.19-25
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• 2001

본 연구에서는 디지털 셀룰러용 IF Frequency Synthesizer의 설계, 시뮬레이션 결과 및 측정 결과를 기술하였으며, 공정 및 소자 라이브러리는 AMS사의 0.8 $\mu\textrm{m}$ BiCMOS를 사용하였다. IF Frequency Synthesizer부는 IF 전압제어발진기, 위상검파기, 8분배기, 차지 펌프 및 루프 필터(Loop Filter) 등을 포함하고 있다. 공급전원은 2.7에서 3.6 V이며, IF VCO의 조절전압은 0.5~2.7V이고, 소비전류는 11 mA로 설계결과와 측정결과가 유사한 결과를 보였다.

• 한국초전도ㆍ저온공학회논문지
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• 제17권3호
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• pp.18-22
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• 2015

This paper deals with high-Tc superconducting (HTS) power charging system with GdBCO magnet, photo-voltaic (PV) controller, and solar panels to charge solar energy. When combining the HTS magnet and the solar energy charging system, additional power source is not required therefore it is possible to obtain high power efficiency. Since there is no resistance in superconducting magnet carrying DC transport current the energy losses caused by joule heating can be reduced. In this paper, the charging characteristics of HTS power charging system was simulated by using PSIM. The charging current of HTS superconducting power charging system is measured and compared with the simulation results. Using the simulation of HTS power charging system, it can be applied to the solar energy applications.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.465-466
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• 2006

In this paper, novel analog duty cycle corrector (DCC) with a digital duty error detector is proposed. The digital duty error detector measures the duty error of the clock and converts it into a digital code. This digital code is then used to accurately correct the duty ratio by adaptively steering the charge-pump current. The proposed duty cycle corrector was implemented using an 80nm DRAM process with 1.8V supply voltage. The simulation result shows that the proposed duty cycle corrector improves the settling time up to $70{\sim}80%$ at 500MHz clock frequency for the same duty correction accuracy as the conventional analog DCC.

• 대한전자공학회논문지SD
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• 제46권2호
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• pp.71-77
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• 2009

본 논문에서는 다중 전하펌프를 이용하여 빠른 위상고정 시간을 갖는 새로운 위상고정루프를 제안하였다. 제안된 위상고정 루프는 세 개의 전하펌프를 사용하여 루프필터의 실효 커패시턴스와 저항을 위상고정 상태에 따라 각 전하펌프의 전류량 크기와 방향 제어를 통해 증감시킬 수 있다. 위상고정루프의 위상고정 상태에 따라 루프 대역폭을 제어하여 빠른 위상고정 시간을 갖는 위상고정루프를 설계하였다. 또한 전체 칩 영역의 많은 부분을 차지하는 커패시터의 크기를 제안된 구조로 최소화하였다. 저항과 커패시터를 모두 포함한 29.9KHz의 대역폭의 위상고정루프를 $990{\mu}m\;{\times}\;670{\mu}m$ 크기로 설계하였다. 제안된 위상고정 루프는 3.3V $0.35{\mu}m$ CMOS 공정을 이용하여 제작되었다. 851.2MHz 출력 주파수에서 측정된 위상 잡음은 -90.45 dBc/Hz@1MHz이며, 위상고정시간은 $6{\mu}s$ 보다 작은 값을 가진다.