• Journal of IKEEE
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• v.19 no.4
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• pp.573-582
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• 2015

This paper presents the design of dual mode boost converter for energy harvesting. The designed converter boosts low voltage from energy harvester through a startup circuit. When the voltage goes above predefined value, supplied voltage to startup circuit is blocked by voltage detector. Boost controller makes the boosted voltage into $V_{OUT}$. The proposed circuit consists of oscillator for charge pump, charge pump, pulse generator, voltage detector, and boost controller. The proposed converter is designed and fabricated using a $0.18{\mu}m$ CMOS process. The designed circuit shows that minimum input voltage is 600mV, output is 3V and startup time is 20ms. The boost converter achieves 47% efficiency at a load current of 3mA.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.7
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• pp.563-566
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• 2009

This paper presents a motor drive IC for automotive applications. The drive IC is dedicated to control and drive external MOSFETs which directly drive 3-phase motor with a high current. In case of driving high-side power switches, the bootstrap topology is widely used. however, it requires three bootstrap diode and three capacitor respectively. And it needs a minimum charging time to maintain high-side voltage. The motor drive IC uses a charge-pump circuit for all three high-side voltage with various protection schemes for automotive applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.41-42
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• 2009

This paper presents a motor drive IC for automotive applications. The drive IC is dedicated to control and drive external MOSFETs which directly drive 3-phase motor with a high current. In case of driving high-side power switches, the bootstrap topology is widely used. However, it requires three bootstrap diode and three capacitor respectively. And it needs a minimum charging time to maintain high-side voltage. The motor drive IC uses a charge-pump circuit for all three high-side voltage with various protection schemes for automotive applications.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.108-112
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• 2002

A new pixel driving method for organic light-emitting diode (OLED) flat-panel display (FPD) is proposed. The new charge-pump passive-matrix pixel driver consists only of a storage capacitance and a rectifying diode, and no thin-film transistor (TFT) is needed. The new driver not only supplies a constant current to the OLED throughout the whole period of panel scanning like an active-matrix driver, but also provides a highly linear gray-scale control through a pure digital manner.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3088-3090
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• 2000

In this paper, we introduce a charge pump PLL architecture which employs precharge phase frequency detector(PFD) and sequential PFD to achieve high frequency operation and fast acquisition. Operation frequency is increased by using precharge PFD when the phase difference is within -${\pi}\;{\sim}\;{\pi}$ and acquisition time is shortened by using sequential PFD and increased charge pump current when the phase difference is larger than |${\pi}$|. SO error detection range of proposed PLL structure is not limited to -${\pi}\;{\sim}\;{\pi}$. By virtue of this multi-phase frequency detector structure, the maximum operating frequency of 423MHz at 2.5V and faster acquisition were achieved by simulation.

• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.82-87
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• 2008

This paper presents a new fast locking dual-slope phase-locked loop. The conventional dual-slope phase-locked loop consists of two charge pumps and two phase-frequency detectors. In this paper, the dual-slope phase-locked loop was achieved with a charge pump and a phase-frequency detector as adjusting a current of the charge pump according to the phase difference. The proposed circuit was verified by HSPICE simulation with a $0.35{\mu}m$ CMOS standard process parameter. The phase locking time of the proposed dual-slope phase-locked loop was $2.2{\mu}s$ and that of the single-slope phase-locke loop was $7{\mu}s$.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• Journal of Sensor Science and Technology
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• v.32 no.6
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• pp.432-440
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• 2023

This study introduces an efficient readout circuit designed for two-electrode electrocardiogram (ECG) recording, characterized by its low-noise and low-power consumption attributes. Unlike its three-electrode counterpart, the two-electrode ECG is susceptible to common-mode interference (CMI), causing signal distortion. To counter this, the proposed circuit integrates a common-mode charge pump (CMCP) with a window comparator, allowing for a CMI tolerance of up to 20 V_PP. The CMCP design prevents the activation of electrostatic discharge (ESD) diodes and becomes operational only when CMI surpasses the predetermined range set by the window comparator. This ensures power efficiency and minimizes intermodulation distortion (IMD) arising from switching noise. To maintain ECG signal accuracy, the circuit employs a chopper-stabilized instrumentation amplifier (IA) for low-noise attributes, and to achieve high input impedance, it incorporates a floating high-pass filter (HPF) and a current-feedback instrumentation amplifier (CFIA). This comprehensive design integrates various components, including a QRS peak detector and serial peripheral interface (SPI), into a single 0.18-㎛ CMOS chip occupying 0.54 mm². Experimental evaluations showed a 0.59 µV_RMS noise level within a 1-100 Hz bandwidth and a power draw of 23.83 µW at 1.8 V.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.86-88
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• 1996

Using superconducting magnetic flux pump, thick power leads for a superconducting magnet could be replaced with thin string leads for the excitation magnet to the superconducting flux pump. We have developed a new type flux pump with high voltage output to shorten the charge and discharge time of the load magnet. The test of four stacked disks as the excither for the load magnet has been carried out. This disk type flux pump yielded 70 mV of voltage across its terminal and 10 A of current through 85 mH load magnet which was the field winding of 20 kVA class fully superconducting generator within 12 seconds. This output voltage of the new superconducting flux pump is about 10 times larger than that of the previous work Moreover since it is easy to stack the disks for the superconduction flux pump, the high voltage exciter for the 1H class superconducting magnet would be expected to be made easily.