• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.499-500
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• 2006

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about $20{\mu}s$. This chip is fabricated with $0.25{\mu}m$ CMOS technology, and the die area is $0.7mm{\times}2.1mm$. The power consumption is 54mW at 2.7V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.517-526
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• 2008

A one-chip DC-DC converter circuit for OLED(Organic Light-Emitting Diode) display module of automotive clusters is newly proposed. OLED panel driving voltage circuit, which is a charge-pump type, has improved characteristics in miniaturization, low cost and EMI(Electro-Magnetic Interference) compared with DC-DC converter of PWM(Pulse Width Modulator) type. By using bulk-potential biasing circuit, charge loss due to parasitic PNP BJT formed in charge pumping, is prevented. In addition, the current dissipation in start-up circuit of band-gap reference voltage generator is reduced by 42% and the layout area of ring oscillator is reduced by using a logic voltage VLP in ring oscillator circuit using VDD supply voltage. The driving current of VDD, OLED driving voltage, is over 40mA, which is required in OLED panels. The test chip is being manufactured using $0.25{\mu}m$ high-voltage process and the layout area is $477{\mu}m{\times}653{\mu}m$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1155-1161
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• 2014

This paper proposes a start-up voltage generator for reducing the minimum input supply voltage of DC-DC boost converters to 250mV. The proposed start-up voltage generator boosts 250mV input voltage to over 500mV to charge the capacitor for starting the boost converter. After the boost converter operates initially with the supply voltage charged in the capacitor, it uses its boosted output voltage for the supply voltage. Therefore, after the start-up operation, the proposed DC-DC boost converter works as the same as the conventional one. The proposed start-up voltage generator reduces the threshold voltage of the transistors by adjusting the body voltage at a low input voltage. This causes the higher clock frequency and the larger current to a Dickson charge-pump for boosting the input voltage. The proposed start-up voltage generator was implemented with a $0.18{\mu}m$ CMOS process. Its clock frequency and output voltage were 34.5kHz and 522mV at 250mV input voltage, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.37-44
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• 2009

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1552-1558
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• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

• Journal of Soil and Groundwater Environment
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• v.20 no.2
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• pp.41-46
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• 2015

The drag of the excess charge in an electrical double layer at the solid fluid interface due to water flow induces the streaming current, i.e., the streaming potential (SP). Here we introduce a sandbox experiment to study this hydroelectric coupling in case of a tracer test. An acrylic tank was filled up with homogeneous sand as a sand aquifer, and the upstream and downstream reservoirs were connected to the sand aquifer to control the hydraulic gradient. Under a steady-state water flow condition, a tracer test was performed in the sandbox with the help of peristaltic pump, and tracer samples were collected from the same interval of five screened wells in the sandbox. During the tracer test, SP signals resulting from the distribution of 20 nonpolarizable electrodes were measured at the top of the tank by a multichannel meter. The results showed that there were changes in the observed SP after injection of tracer, which indicated that the SP was likely to be related to the solute transport.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.13-21
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• 2010

A energy efficient $V_{pp}$ generator using a variable pumping frequency for mobile DRAM is presented in this paper. The proposed $V_{pp}$ generator exploits 3 stages of a cross-coupled charge pump for energy efficiency. Instead of using a fixed pumping frequency in the conventional $V_{pp}$ generator, our proposed $V_{pp}$ generator adopts a voltage-controlled oscillator and uses variable frequencies to reduce the ramp-up time. As a result, our $V_{pp}$ generator generates 3.0 V output voltage with 24.0-${\mu}s$ ramp-up time at 2 mA current load and 1 nF capacitor load with 1.2 V supply voltage. Experimental results show that the proposed $V_{pp}$ generator consumes around 26% less energy (1573 nJ $\rightarrow$ 1162 nJ) and reduces 29% less ramp-up time (33.7-${\mu}s$ $\rightarrow$ 24.0-${\mu}s$) compared to the conventional approach.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.941-947
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• 2017

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.