• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.12C
• /
• pp.261-267
• /
• 2001

This paper presents the architecture of multiple-queue manager for input-queued switch, which has arbitration latency, and the design of the chip. The proposed architecture of multiple-queue manager provides wire-speed routing with a pipelined buffer management, and the tolerance of requests and grants data transmission latency between the input queue manager and central arbiter using a new request control method, which is based on a high-speed shifter. The multiple-input-queue manager has been implemented in a field programmable gate array chip, which provides OC-48c port speed. It enhances the maximum throughput of the input queuing switch up to 98.6% with 128-cell shared input buffer in 16$\times$16 switch size.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.20 no.3
• /
• pp.129-134
• /
• 2020

Moisture infiltration inside the solar cell module, filling of EVA sheet, melting of the frame seal, and deterioration of power generation performance in the module one year after installation are occurring. Whitening phenomenon, electrode corrosion phenomenon, and dielectric breakdown phenomenon are appearing in solar cell module installed in Korea before 5-7 years, leading to deterioration of power generation performance, and big problems for long-term reliability and long life technology are emerging. Therefore, in order to solve these problems, the development of a micro inverter (MiCrco Inverter Converter, MiC) including the function of securing the durability of the solar cell module and monitoring the aging progress and the solar cell based on the monitoring data from the MiC smart monitoring programs have been proposed to determine the aging of modules. In addition, in order to become a highly efficient solar smart monitoring system through systematic operation management through IT convergence with MiC that has enhanced monitoring function of solar cell module, SoC(System On Chip) in micro inverter is the environment for solar cell module. There is a demand for functions that can detect information in a complex manner and perform communication and control when necessary. Based on these requirements, this paper aims to develop SoC-based low-cost MiC smart photovoltaic system technology.

• Journal of the Korean Society of Manufacturing Technology Engineers
• /
• v.23 no.1
• /
• pp.32-37
• /
• 2014

Open-cell silicon foam is difficult to cut using conventional machining processes because of its low stiffness. That is, open-cell silicon foam is easily pressed down when the tool is engaged, which makes it difficult to remove the material in the form of chip. This study proposes an advanced method of machining open-cell silicon foam by freezing the material using liquid nitrogen. Furthermore, the machining conditions are optimized to maximize the efficiency of material removal and minimize the usage of liquid nitrogen by conducting experiments under various machining conditions. The results show that open-cell silicone foam products with free surface can be successfully machined by employing the proposed method.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.2
• /
• pp.26-36
• /
• 1999

In this paper, the novel scheme of OAM performance management function is proposed to supply the most of network resources and reliable services by processing data having various QoS(quality of service) in the view of cell loss and cell delay of ATM networks Also, the special fields of OAM cell are defined in order to improve correlate control, operation, and management technique between networks which is required to flexibility and precision control as detecting the performance information of the variable networks periodically. The proposed OAM function, the input/output function of cell, and the interface function of the accessory device which is likely to the memory/CPU are designed to ASIC. The designed chip is carried out the back-end simulation using Verilog-XL simulator of Cadence. In result, it is able to performs an accurate control in $2{\mu}s$.

• 전자공학회논문지 IE
• /
• v.48 no.2
• /
• pp.6-11
• /
• 2011

This paper describes the design of new method of propagation delay measurement in micro and nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell (NOR, AND, XOR, etc.) to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation, we can make assumptions about accuracy and quality of the transistor's parameters. Physical implementation of phase error accumulation method(PHEAM) can be easy integrated at the same chip as close as possible to the device under test(DUT). It was implemented as digital IP core for semiconductor manufacturing process($0.11{\mu}m$, GL130SB). Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic-to-parameters extraction (STPE), basic cell layout verification, design simulation and verification are announced.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.10 s.340
• /
• pp.1-8
• /
• 2005

In this paper, a FRAM design style based on PMOS-gating cell structure is described. The memory cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) $V_{DD}$ precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore, Because this configuration doesn`t need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation for a 2.5-V, 1-Mb FRAM prototype design in a $0.25-{\mu}m$, triple-well technology shows a chip size of $3.22\;mm^{2}$, an access time of 48 ns and an active current of 11 mA. The cell efficiency is 62.52 $\%$. It has gained approximately $20\;\%$ improvement in the cell array efficiency over the conventional plate-driven FRAM scheme.

• Proceedings of the Korean Society for Bioinformatics Conference
• /
• 2000.11a
• /
• pp.41-44
• /
• 2000

With the advent of DNA microarray and "chip" technologies, gene expression in an organism can be monitored on a genomic scale, allowing the transcription levels of many genes to be measured simultaneously. Functional interpretation of massive expression data and linking such data to DNA sequences have become the new challenges to bioinformatics. I will us yeast cell cycle expression data analysis as an example to demonstrate how special database and computational methods may be used for extracting functional information, I will also briefly describe a novel clustering algorithm which has been applied to the cell cycle data.

• International Journal of Control, Automation, and Systems
• /
• v.2 no.2
• /
• pp.135-143
• /
• 2004

Recently, high throughput screening for microorganisms with desired characteristics from a large heterogeneous population has become possible. Single cell separation has taken on increasing significance in recent years, and several different methods have been proposed so far. In this paper, we introduce several cell manipulation methods aiming at single cell separation and investigation. At first, methods for the separation of microorganisms are classified. Then, we introduce two different approaches, that is, (1) indirect manipulation using laser trapped microtools and (2) thermal gelation.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.32 no.10
• /
• pp.844-849
• /
• 2008

We present a novel cell deformability monitoring chip based on the digitally measured cell lysis rate which is dependent on the areal strain of the cell membrane. This method offers simple cell deformability monitoring by automated high-throughput testing system. We suggest the filter design considering the areal strain imposed on the cell membrane passing through the filter array having gradually increased orifice length. In the experiment using erythrocytes, we characterized the cell deformability in terms of average fracture areal strain which was $0.24{\pm}0.014\;and\;0.21{\pm}0.002$ for normal and chemically treated erythrocytes, respectively. We also verified that the areal strain of 0.15 effectively discriminates the deformability difference of normal and chemically treated erythrocytes, which can be applied to the clinical situation. We compared the lysis rates and their difference for the samples from different donors and found that the present chips can be commonly used without any calibration process. The experimental results demonstrate the simple structure and high performance of the present cell deformability monitoring chips, applicable to simple and cost-effective cell aging process monitoring.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2022.10a
• /
• pp.459-461
• /
• 2022

One of the big differences between Network-on-Chip (NoC) and the existing parallel processing system based on an off-chip network is that data packet routing is performed using a centralized control scheme. In such an environment, the best-effort packet routing problem becomes a real-time assignment problem in which data packet arriving time and processing time is the cost. In this paper, the Hungarian algorithm, a representative computational complexity reduction algorithm for the linear algebraic equation of the allocation problem, is implemented in the form of a hardware accelerator. As a result of logic synthesis using the TSMC 0.18um standard cell library, the area of the circuit designed through case analysis for the cost distribution is reduced by about 16% and the propagation delay of it is reduced by about 52%, compared to the circuit implementing the original operation sequence of the Hungarian algorithm.