• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.221-225
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• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

• 전기학회논문지
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• 제56권1호
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• pp.88-99
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• 2007

In this paper, a novel new pulse power generator based on IGBT stacks is proposed for pulse power application. Because it can generate up to 60kV pulse output voltage without any step- up transformer or pulse forming network, it has advantages of fast rising time, easiness of pulse width variation and rectangular pulse shape. Proposed scheme consists of series connected 9 power stages to generate maximum 60kV output pulse and one series resonant power inverter to charge DC capacitor voltage. Each power stages are configured as 8 series connected power cells and each power cell generates up to 850VDC pulse. Finally pulse output voltage is applied using total 72 series connected IGBTs. To reduce component for gate power supply, a simple and robust gate drive circuit is proposed. For gating signal synchronization, full bridge invertor and pulse transformer generates on-off signals of IGBT gating with gate power simultaneously and it has very good characteristics of short circuit protection.

• 전자공학회논문지A
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• 제30A권12호
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• pp.18-27
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• 1993

In this paper, the concept of sampling vectors is introduced, and used for a simple realization of DSSs(distributed sample scramblers). In DSSs, if the sampling times of the scrambler state samples are not identical to their transmission times, samples are delayedtransmitted to the descrambler. and in this case the DSSs need additional memory elements storing the samples and additional clocks for informing their transmission times. The concept of sampling vectors helps move the sampling times of delayed samples to their transmission times, thus eliminating the additional memory elements and clocks in the DSSs. In the paper, the conditions on the synchronization of the scrambler and descrambler are derived for the DSS employing sampling vectors,and demonstrations are given on their applicaitons to cell-based ATM DSSs.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.54-56
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• 2005

The paper proposes the solar photovoltaic power generation system method for photovoltaic system to solve the power shortage due the sudden power demand. So that supplied electric power to system at appearance during surplus electric power minute and unit moment link driving with common use system is available, digital PLL circuit system voltage through composition and phase of solar photovoltatic power generation system to do synchronization do. Feed forward controller was applied to get fast current response Solar cell that is changed by solar radiation always kept the maximum output when it used Step up chopper. The dynamic character had checked through simulation used Matlab Sumulink and confirmed through an experiment.

• ETRI Journal
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• 제33권4호
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• pp.633-636
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• 2011

In this letter, we propose an overlaid hybrid division duplex (HDD) concept for cellular systems which divides a cell into inner and outer regions and utilizes the merits of both time division duplex (TDD) and frequency division duplex (FDD). The proposed system can take advantage of both TDD and FDD without handover between two duplex schemes. Moreover, it is shown that the proposed HDD system outperforms the conventional TDD or FDD system with mobile relay stations when the synchronization issue is considered in orthogonal frequency division multiple access systems. Thus, the proposed overlaid HDD can be considered as a new framework for future cellular systems.

• 전자공학회논문지C
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• 제34C권12호
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• pp.9-19
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• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 전력전자학술대회 논문집
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• pp.53-54
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• 2014

MMC(Modular Multilevel Converter)는 여러 개의 Power Module을 직렬로 연결하여 정현파에 가까운 고전압의 파형을 얻을 수 있는 토폴로지로 대용량 전력변환 분야의 요구를 만족하면서 전력 품질을 향상시킬 수 있어 근래에 상당히 주목받고 있다. 당사에서는 5Mvar급 STATCOM(STATic synchronization COMpensator)을 MMC 형태로 제작하였다. 1개의 Cell 제어기는 6대의 Power Module의 제어와 보호를 담당하여 DC 전압을 센싱하여야 한다. 본 논문에서는 제안한 SPI(Serial Peripheral Interface) 통신을 이용하여 Power Module을 제어하기 위해 DC 센싱 방법에 대해 설명한다.

• 한국통신학회논문지
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• 제37A권12호
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• pp.1076-1084
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• 2012

CS/CB(Coordinated Scheduling/Beamforming) 방식은 인접 기지국으로부터의 간섭신호를 최소화시키는 MIMO(Multiple Input Multiple Output) 프리코더를 선택함으로써 셀 경계 사용자의 수율을 증가시킨다. 그러나 현재의 LTE(Long Term Evolution) 시스템에서는 안테나 한 개를 사용하여 주위 기지국으로부터 전송된 동기신호와 기준신호를 사용하여 초기화 단계에서 서빙 셀이 선택된다. 이와 같이 선택된 셀은 초기화 단계에서 MIMO 프리코더 이득을 고려하지 않고 선택되었기 때문에 데이터 전송시 최적의 선택이 아닐 수 있다. 본 논문에서는 MIMO 프리코더를 갖는 LTE 시스템을 위하여 초기화 단계에서 프리코더의 영향을 고려하여 셀을 선택하는 기법을 제안한다. 제안된 기법은 후보 기지국들에서 전송한 기준신호를 사용하여 획득한 정보(랭크, 유효 채널 용량, 유효 SINR(Signal to Interference plus Noise Ratio))를 사용하여 셀 경계의 단말이 서빙 기지국을 선택할 수 있도록 한다. 제안한 기법은 기존의 기법과 비교하여 다중 셀 환경하의 LTE 시스템에서 채널 용량을 크게 향상시킬 수 있음을 모의실험을 통하여 확인한다.

• 한국동물번식학회:학술대회논문집
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• 한국동물번식학회 2001년도 춘계학술발표대회
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• pp.69-69
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• 2001

The cell cycle phase in which donor nuclei exist prior to nuclear transfer is an important factor governing developmental rates of reconstituted embryos. It was suggested that quiescent G0 and cycling G1 cells could support normal development of reconstituted embryos. In a quest of optimized donor nuclei treatment prior to nuclear transfer, this study was undertaken to examine the cell cycle characteristics of bovine fetal and adult somatic cells when cultured under a variety of culture treatments and the cell cycle change with the lapse of time after trypsinization. This was archived by measuring the DNA content of cells using flow cytometry, Cultured fetal fibroblast cells, adult skin and muscle cells, and cumulus cells were divided by 3 culture treatments; 1) grown to 60-70% confluency (cycling), 2) serum starved culture, 3) culture to confluency. Trypsinized cells were fixed by 70% ethanol and stained with propidium iodide. For one experiment, trypsinized cells were resuspended in DMEM＋10% FBS and incubated for 1.5, 3 and 6 h with occasional shaking before ethanol fixation. Cell cycle phases were determined by flow cytometry enabling calculation of percentages of G0＋G1, S and G2＋M. The majority of cells were in G0＋Gl stage regardless of origin of cells. Cultures that were serum starved or cultured to confluency contained significantly (P<0.05) higher percentages of cells in G0＋G1 (89.5-95.4%). For every cell lines and culture treatments, percentages of cells in existing in G0＋G1 increased with decreasing of the cell size from large to small. In the serum starved and confluency groups, about 98% of small cells were in G0＋G1 Serum starved culture contained higher percentages of small-sized cells (38.5-66.9%) than cycling and confluent cultures regardless of cell lines (P<0.05). After trypsinization of fetal fibroblast and adult skin cells that were serum starved and cultured to confluency, the percentages of cells in G0＋G1 significantly increased by incubation for 1.5(95.7-99.5%) and 3.0 h (95.9-98.6%). The results suggest that the efficient synchronization of bovine somatic cells in G0＋G1 for nuclear transfer can be established by incubation for a limited time period after trypsinization of serum starved or confluent cells.

• 한국통신학회논문지
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• 제36권6A호
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• pp.558-567
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• 2011

본 논문에서는 Type 1 relay를 이용하는 3GPP (3rd Generation Pattnership Project) LTE Long Term Evolution)-Advanced 시스템을 위한 부분 전이중 (partial full duplex) relay 기법을 제안한다. Type 1 relay는 백홀 링크 (backhaul link)와 액세스 링크 (access link)가 같은 대역을 이용하는 inband relay로 동시에 백홀 링크와 액세스 링크에서 송수신 하는 경우에 self-interference가 발생하여 수신 성능이 크게 열화되기 때문에 동시에 송수신할 수 없다. 이와 같은 특징 때문에 Type 1 relay는 eNB (evolved NodeB)가 동기 신호를 송신할 때, 자신에게 접속하고 있는 R-UE (Relay-User Equipment)에게 동기 신호를 송신해야 하는 특정에 의해서 eNB가 송신하는 동기 신호를 수신할 수 없어 셀 ID (Identity)를 검출할 수 없는 문제점을 갖는다. 따라서, 이러한 문제점을 해결하기 위하여 본 논문에서는 eNB와 Type 1 relay가 동기 신호를 송신하는 subframe에서만 Type 1 relay가 동시에 송수신하는 부분 전이중 relay 기법을 제안한다. 또한, 동시에 Type 1 relay가 백홀 링크와 액세스 링크에서 송수신하여 발생하는 self-interference를 제거하기 위하여 Type 1 relay의 송수신 안테나 사이의 공간적 분리 (geometric isolation)와 SIC (Self-Interference Cancellation) 방식을 적용하고, SIC의 성능을 높이기 위한 정확한 채널 추정 방안으로 부분 채널 추정 (partial channel estimation) 기법을 제안하며, 다양한 환경에서의 성능 평가를 통해 제안된 방식이 Type 1 relay를 이용하는 3GPP LTE-Advanced 시스템에서 매우 유용한 것을 입증하였다.