• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.295-298
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• 2003

Reflective mode liquid crystal on silicon (LCoS) microdisplay is the major technology that can produce extremely high-resolution displays. A very large number of pixels can be packed onto the CMOS circuit with integrated drivers that can be projected to any size screen. Large size direct-view thin film transistor (TFT) LCDs becomes very difficult to make and to drive as the information content increases. However, the existing LC alignment technology for the LCoS cell fabrication is still the mechanical rubbing method, which is prone to have minor defects that are not visible normally but can be detrimental if projected to a large screen. In this paper, application of photo-alignment to LCoS fabrication is presented. The alignment is done by three-step exposure process. A MTN $90^{\circ}$ mode is chose as to evaluate the performance of this technique. The comparison with rubbing mode shows the performance of photo-alignment is comparable and even better in some aspect, such as sharper RVC curve and higher contrast ratio.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.159-159
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• 2008

투명전도체 (transparent conducting oxides: TCOs) 는 일반적으로 $10^3\Omega^{-1}Cm^{-1}$의 전도도, 가시광 영역에서 80%이상의 투명성을 가지는 재료로서, 액정 박막 표시 장치(TFT-LCD), 광기전성 소자, 유기 발광 소자, 에너지 절약 창문, 태양전지(sollar cell) 등 전극으로 사용되고 있다. 최근에는 TCO의 전도도특성을 조절하여 반도성특성을 가진 투명 산화물 반도체(transparent oxide semiconductor: TOS) 을 이용한 박막 트랜지스터 연구가 활발히 진행 중이다. 기존의 실리콘을 기반으로 하는 박막 트랜지스터의 낮은 이동도, 불투명성의 특성을 가지고 있지만, 산화물 박막트랜지스터는 높은 이동도를 발현 할 수 있을 뿐만 아니라, 넓은 밴드갭 에너지를 갖는 산화물을 이용하므로 투명한 특성도 발현 할 수 있어 차세대 디스플레이의 구동소자로서 응용연구가 되고 있다. 이에 본 연구에서는 박막트랜지스터 channel layer로서의 Indium-Tin-Zinc oxide 적용특성을 조사하였다. Indium, Tin, Zinc 의 혼합비율을 다양하게 조절하여 타겟을 제작하였다. 이를 RF magnetron sputtering 를 이용하여 박막으로 성장시켰으며, 기판으로는 glass 기판을 사용하였다. 박막 성장시 아르곤과 산소의 비율을 다양하게 조절하였다. 성장시킨 박막은 Hall effect, Transmittance, Work function, XRD등을 이용하여 전기적, 광학적, 구조특성을 평가하였다. Indium-Tin-Zinc Oxide(ITZO) 을 channel layer로 사용하여 Thin-film transistor 을 제작하여, TFT의 I-V 및 stability특성을 평가하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1054-1057
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• 2002

The design and fabrication of Q-band 3-stage monolithic microwave integrated circuit(MMIC) amplifier for WLAN are presented using 0.2$\square$ AIGaAs/lnGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT). In each stage of the MMIC, a negative feedback is used for both broadband and good stability. The measurement results are achieved as an input return loss under -4dB, an output return loss under -10dB, a gain of 14dB, and a PldB of 17dBm at Q-band(36～44GHz). These results closely match with design results. The chip size is 2.8${\times}$1.3mm$^2$. This MMIC amplifier will be used as the unit cell to develop millimeter-wave transmitters for use in wideband wireless LAN systems.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.185-196
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• 2002

MRAM(magnetic random access memory) is a promising candidate for a universal memory with non-volatile, fast operation speed and low power consumption. The simplest architecture of MRAM cell is a combination of MTJ(magnetic tunnel junction) as a data storage part and MOS transistor as a data selection part. This article will review the general development status of MRAM and discuss the issues. The key issues of MRAM technology as a future memory candidate are resistance control and low current operation for small enough device size. Switching issues are controllable with a choice of appropriate shape and fine patterning process. The control of fabrication is rather important to realize an actual memory device for MRAM technology.

• Journal of electromagnetic engineering and science
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• 제17권4호
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• pp.178-180
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• 2017

This study presents a 2-20 GHz monolithic distributed power amplifier (DPA) using a $0.25{\mu}m$ AlGaN/GaN on SiC high electron mobility transistor (HEMT) technology. The gate width of the HEMT was selected after considering the input capacitance of the unit cell that guarantees decade bandwidth. To achieve high output power using small transistors, a 12-stage DPA was designed with a non-uniform drain line impedance to provide optimal output power matching. The maximum operating frequency of the proposed DPA is above 20 GHz, which is higher than those of other DPAs manufactured with the same gate-length process. The measured output power and power-added efficiency of the DPA monolithic microwave integrated circuit (MMIC) are 35.3-38.6 dBm and 11.4%-31%, respectively, for 2-20 GHz.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2010년도 춘계학술발표대회
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• pp.19.1-19.1
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• 2010

The process of manufacturing printed electronics using printing technology is attracting attention because its process cost is lower than that of the conventional semiconductor process. This technology, which offers both a lower cost and higher productivity, can be applied in the production of organic TFT (thin film transistor), solar cell, RFID(radio frequency identification) tag, printed battery, E-paper, touch screen panel, black matrix for LCD(liquid crystal display), flexible display, and so forth. In general, in order to implement printed electronics, narrow width and gap printing, registration of multi-layer printing by several printing units, and printing accuracy of under $20\;{\mu}m$ are all required. These electronic products require high precision to the degree of tens of microns - in a large area with flexible material, and mass productivity at low cost. As such, the roll-to-roll printing process is attracting attention as a mass production system for these printed electronic devices. For the commercialization of this process, two basic electronic ink technologies, such as conductive ink and polymers, and printing equipment have to be developed. Therefore, this paper addressed basis design and test to develop fine patterning equipment employing the roll-to-roll printing equipment and electronic ink.

• 대한화학회지
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• 제60권3호
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• pp.194-202
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• 2016

Two conjugated semiconducting copolymers consisting of 4,7-bis(4-(2-ethylhexyl)-2-thiophene)-2,1,3-benzothiadiazole (DTBT) and benzo[1,2-b:4,5-b']dithiophene with 5-(2-ethylhexyl)-2,2'-bithiophene (BDTBT) or 5-(2-ethylhexylthio)- 2,2'-bithiophene (BDTBT-S) were designed and synthesized as donor materials for organic photovoltaic cells (OPVs). Alkylthio-substituted PBDTBT-S-DTBT showed a higher hole mobility and lower highest occupied molecular orbital (HOMO) energy level (by 0.08 eV) than the corresponding alkyl-substituted PBDTBT-DTBT. An OPV fabricated using PBDTBT-S-DTBT showed higher V_OC and J_SC values of 0.83 V and 7.56 mA/cm², respectively, than those of a device fabricated using PBDTBT-DTBT (0.74 V) leading to a power conversion efficiency of 2.05% under AM 1.5G 100 mW/cm² illumination.

• 대한전자공학회논문지
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• 제21권5호
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• pp.67-78
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• 1984

프로팅 게이트 위에 컨트롤 게이트를 갖는 n-채널 이중 다결정 실리콘게이트 EAROM을 제작하였다. 채널 길이는 4-8μm, 채널 폭은 5-14μm로 하여 5μm design rule에 따라 설계하였으며 서로 다른 4가지 컨트롤게이트 구조를 갖는 채널 주입형 기억소자를 얻었다. 그리고 소자의 Punch through 전압과 게이트에 의해 조절되는 채널파괴 전압을 증가시키기 위해 이중 이온주입 (double ion implantation)과 active 영역에 보론이온을 주입 하였다. 프로그래밍을 위해 드레인 전압 및 게이트 전압이 각각 13-l7V 및 20-25V 정도 필요하였다. 그리고 제조된 기억소자의 소거는 광학적 방법뿐 아니라 전기적 방법으로도 가능하였으며 125℃에서 200시간 유지하였을 때 축적된 전자가 약 4 %정도 감소함을 알 수 있었다.

• 한국전기전자재료학회논문지
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• 제13권10호
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

• 한국전기전자재료학회논문지
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• 제28권4호
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• pp.218-221
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• 2015

Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. In this study we have investigated a structure to reduce the on-resistance characteristics of the MOSFET. We have a proposed MOSFET structure of active cells region buried under the gate pad. The measurement are carried out with a EDS to analyze electrical characteristics, and the proposed MOSFET are compared with the conventional MOSFET. The result of proposed MOSFET was 1.68[${\Omega}$], showing 10% improvement compared to the conventional MOSFET at 700[V].