• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.1
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• pp.101-108
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• 2005

Adaptive constant false alarm rate(CFAR) algorithm is used for good detection probability as well as constant false alarm rate in clutter background. Especially, filtering technique adaptive to spatial variation is necessary for improving detection quality in non stationary clutter environment which has spatial correlation and large magnitude deviation. In this paper, we propose a two-dimensional block interpolation(TBI) adaptive CFAR algorithm that calculates the node estimate in the fred two dimensional region and subsequently determines the final estimate for each resolution cell by two-dimensional interpolation. The proposed method is efficient for filtering abnormal ejection by adopting distribution median in fixed region and also has advantage of reducing required memory space by using estimation method which gets final values after calculating the block node values. Through simulations, we show that the proposed method is superior to the traditional adaptive CFAR algorithms which are transversal or recursive in aspect of the detection performance and required memory space.

• Journal of IKEEE
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• v.22 no.1
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• pp.38-45
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• 2018

An integrated cryptographic processor that efficiently integrates ARIA, AES block ciphers and Whirlpool hash function into a single hardware architecture is described. Based on the algorithm characteristics of ARIA, AES, and Whirlpool, we optimized the design so that the hardware resources of the substitution layer and the diffusion layer were shared. The round block was designed to operate in a time-division manner for the round transformation and the round key expansion of the Whirlpool hash, resulting in a lightweight hardware implementation. The hardware operation of the integrated ARIA-AES-Whirlpool crypto-processor was verified by Virtex5 FPGA implementation, and it occupied 68,531 gate equivalents (GEs) with a 0.18um CMOS cell library. When operating at 80 MHz clock frequency, it was estimated that the throughputs of ARIA, AES block ciphers, and Whirlpool hash were 602~787 Mbps, 682~930 Mbps, and 512 Mbps, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.427-433
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• 2002

This paper describes a design of cryptographic processor that implements the AES(Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation, the round block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.-V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1993-1999
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• 2011

This paper describes a design of area-efficient/low-power cryptographic processor for HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a 0.35-${\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.9
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• pp.5776-5782
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• 2014

Relay-assisted wireless communication systems have been studied widely to cope with shadow areas and extend the cell coverage. This paper proposes a space-frequency (SF) block coded single carrier-frequency division multiple access (SC-FDMA) transmission system in a relaying multi-path shadow area and present the performance comparison of SC-FDMA systems based on the signal-to-noise power ratio (SNR) between a relay and a destination station. The performance of relaying SC-FDMA systems can be improved by applying SF block code to the recovered signals of relays before re-transmitting them. The simulation result showed that the SNR performance of the proposed SF block coded relaying SC-FDMA system was approximately 5 dB better than the SNR performance of the single-path relaying SC-FDMA system at a symbol error rate (SER) of $10^{-2}$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.53-58
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• 2008

This paper designs sigma-delta D/A Converter with a high resolution and low power consumption. It reorganizes the input data along LJ, RJ, I2S mode and bit mode to the output data of A/D converter. The D/A converter decodes the original analog signal through HBF, Hold and 5th CIFB(Cascaded Integrators with distributed Feedback as well as distributed input coupling) sigma-delta modulation blocks. It uses repeatedly the addition operation in instead of the multiply operation for the chip area and the performance. Also, the half band filters of similar architecture composed the one block and it used the sample-hold block instead of the sinc filter. We supposed simple D/A Converter decreased in area. The filters of the block analyzed using the matlab tool. The top block designed using the top-down method by verilog language. The designed block is fabricated using Samsung 0.35um CMOS standard cell library. The chip area is 1500*1500um.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.125-128
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• 2011

This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Applied Microscopy
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• v.51
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• pp.20.1-20.12
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• 2021

We explored the link between mitochondrial biogenesis and mitochondrial morphology using transmission electron microscopy (TEM) in lymphoblasts of pediatric acute lymphoblastic leukemia (ALL) patients and compared these characteristics between tumors and control samples. Gene expression of mitochondrial biogenesis markers was analysed in 23 ALL patients and 18 controls and TEM for morphology analysis was done in 15 ALL patients and 9 healthy controls. The area occupied by mitochondria per cell and the cristae cross-sectional area was observed to be significantly higher in patients than in controls (p-value=0.0468 and p-value<0.0001, respectively). The mtDNA copy numbers, TFAM, POLG, and c-myc gene expression were significantly higher in ALL patients than controls (all p-values<0.01). Gene Expression of PGC-1α was higher in tumor samples. The analysis of the correlation between PGC-1α expression and morphology parameters i.e., both M/C ratio and cristae cross-sectional area revealed a positive trend (r=0.3, p=0.1). The increased area occupied by mitochondria and increased cristae area support the occurrence of cristae remodelling in ALL. These changes might reflect alterations in cristae dynamics to support the metabolic state of the cells by forming a more condensed network. Ultrastructural imaging can be useful for affirming changes occurring at a subcellular organellar level.

• Korean Journal of Biological Psychiatry
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• v.4 no.2
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• pp.211-217
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• 1997

The Bcl-2 protein has been shown to block apoptosis induced by a variety of stimuli. We have performed the experiments which cell death can be blocked by the bcl-2 proto-oncogene under moderate(50-100mM) or high ethanol treatment(400-600mM). As a result of morphological changes, and MTT assay, cell death was blocked by Bcl-2 under 100mM ethanol. However, the results of DNA fragmentation and RT-PCR(ICE, and CPP32), immunoblotting(CPP32, and PARP) for SK-pcDNA3 cells(vector only) and SK-Bcl-2 cells(stably expressed bcl-2 gene) were showen to be no significant differences between two cell lines. These results suggested that cell death induced by ethanol was not followed by apoptosis mechanism, and was blocked by the bcl-2 proto-oncogene with moderate ethanol.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.5
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• pp.432-437
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• 2008

This paper proposes a defect cell extraction algorithm for TFT-LCD auto-repair system. Auto defect search algorithm and automatic defect cell extraction method are very important for TFT-LCD auto repair system. In the previous literature[1], we proposed an automatic visual inspection algorithm of TFT-LCD. Based on the inspected information(defect size and defect axis, if defect exists) by the automatic search algorithm, defect cells should be extracted from the input image for the auto repair system. For automatic extraction of defect cells, we used a novel block matching algorithm and a simple filtering process in order to find a given reference point in the LCD cell. The proposed defect cell extraction algorithm can be used in all kinds of TFT-LCD devices by changing a stored template which includes a given reference point. Various experimental results show the effectiveness of the proposed method.