• The KIPS Transactions:PartA
• /
• v.17A no.6
• /
• pp.275-280
• /
• 2010

In this paper, we discuss and propose an efficiently parallelized block cipher algorithm on the CELL BE processor. With considering the heterogeneous feature of the CELL BE architecture, we apply different encoding/decoding methods to PPE and SPE and improve the throughput. Our implementation was fully tested, with execution results showing achievement of high throughput, capable of supporting as high network speed as 2.59 Gbps. Compared to various parallel implementations on multi-core systems, our approach provides speedup of 1.34 in terms of encoding/decoding speed.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.4A
• /
• pp.447-457
• /
• 2004

This paper proposes a RSA crypto-processor for embedded systems. The architecture of the RSA crypto-processor should be used relying on Big Montgomery algorithm, and is supported by configurable bit size. The RSA crypto-processor includes a RSA control signal generator, an optimal Big Montgomery processor(adder, multiplier). We use diverse arithmetic unit (adder, multiplier) algorithm. After we compared the various results, we selected the optimal arithmetic unit which can be connected with ARM core-processor. The RSA crypto-processor was implemented with Verilog HDL with top-down methodology, and it was verified by C language and Cadence Verilog-XL. The verified models were synthesized with a Hynix 0.25${\mu}{\textrm}{m}$, CMOS standard cell library while using Synopsys Design Compiler. The RSA crypto-processor can operate at a clock speed of 51 MHz in this worst case conditions of 2.7V, 10$0^{\circ}C$ and has about 36,639 gates.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.2 no.4
• /
• pp.583-592
• /
• 1998

In this paper, the cell loss rate is analyzed in terms of the input traffic stream of different speed in ATM network. The cell loss rate is calculated by birth-death process of Leaky-Bucket mechanism as the representative algorithm of usage parameter control. The cell loss rate assumed 2-state MMPP input process to be birth-death process by considering the character of token pool about finite capacity queue. The results from numerical analysis show that the cell loss rate decreases abruptly according to the buffer size increase. The computer simulation by SIMSCRIPT II.5 has been done and compared with on/off input source case to verify the analysis results.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.13 no.6
• /
• pp.469-475
• /
• 2008

In this paper, control of small PEM(Proton Exchange Membrane) fuel cell stack by a microprocessor is introduced. The water management of fuel cell stack inside, a key technique in fuel cell control, can be achieved by adjusting the required air flow for fuel and cooling, and by purging the excessive water from the stack. It is very important to precisely control the BOS(Balance of Stack) since the stable operation of the fuel cell system mainly depends on it. In this study the fuel efficiency of the system is improved by the control of the system based on the measured air flow and purge cycle during the optimal operation and its effectiveness is proved by the experiments. The operating stability of the system is improved by the developed controller using a microprocessor and it is expected to be widely used for the control of small PEM fuel cell stack.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.1
• /
• pp.15-23
• /
• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.2
• /
• pp.283-290
• /
• 2006

The cellular neural networks have the structure that consists of an array of the same cell which is a simple processing element, and each of the cells has local connectivity and space invariant template properties. So, it has a very suitable structure for the hardware implementation. But, it is impossible to have a one-to-one mapping between the CNN hardware processors and the pixels of the practical large image. In this paper, a $5{\times}5$ CNN hardware processor with pipeline input and output that can be applied to the time-multiplexing processing scheme, which processes the large image with a small CNN cell block, is designed. the operation of the implemented $5{\times}5$ CNN hardware processor is verified from the edge detection and the shadow detection experimentations.

• Transactions of the Korean hydrogen and new energy society
• /
• v.27 no.5
• /
• pp.485-493
• /
• 2016

Recently submarine and unmanned underwater vehicle (UUV) are equipped with a fuel cell system as an air independent propulsion system. Methanol fuel processor can efficiently supply the hydrogen to the fuel cell system to improve the ability to dive. This study investigated the optimal conditions of the methanol fuel processor that may be used in the closed environment. For this purpose, the numerical model based on Gibbs minimization equation was established for steam reformer and three exhaust gas burners. After simulating the characteristics of steam reformer according to the steam-to-carbon ratio (SCR) and the pressure change, the SCR condition was able to narrow down to 1.1 to 1.5. Considering water consumption and the amount of heat recovered from three burners, the optimum condition of the SCR can be determined to be 1.5. Nevertheless, the additional heat supply is required to satisfy the heat balance of the methanol fuel processor in the SCR=1.5. In other to obtain additional amount of heat, the combustion of methanol is better than the increased of SCR in terms of system design.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.1
• /
• pp.51-58
• /
• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.8
• /
• pp.1424-1433
• /
• 2007

In this paper, we propose a hardware architecture to generate digital hologram using the modified CGH (Computer Generated Hologram) algorithm for hardware implementation and design to FPGA (Field Programmable Gate Array) platform. After analyzing the CGH algorithm, we propose an architecture of CGH cell which efficiently products digital hologram, and design CGH Kernel from configuring CGH Cell. Finally we implement CGH Processor using CGH Kernel, SDRAM Controller, DMA, etc. Performance of the proposed hardware can be proportionally increased through simply addition of CGH Cell in CGH Kernel, since a CGH Cell has operational independency. The proposed hardware was implemented using XC2VP70 FPGA of Xilinx and was stably operated in 200MHz clock frequency. It take 0.205 second for generating $1,280{\times}1,024$ digital hologram from 3 dimensional object which has 40,000 light sources.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.4C
• /
• pp.388-397
• /
• 2002

We designed a SIMD-DSP/FPU that can efficiently improve multimedia processing performance when integrated into high-performance embedded microprocessors. We proposed partitioned architectures and new schemes for several functional units to reduce chip area. Sharing functional units reduces the area of FPU significantly. The proposed architecture is modeled in HDL and synthesized with a 0.35$\mu\textrm{m}$ standard cell library. The chip area is estimated to be about 100,000 equivalent gates. The designed unit can run at higher than 50MHz clock frequency of CPU core under the worst-case operating conditions.