• 제목/요약/키워드: Cavities

검색결과 1,281건 처리시간 0.025초

A System-in-Package (SiP) Integration of a 62GHz Transmitter for MM-wave Communication Terminals Applications

  • Lee, Young-Chul;Park, Chul-Soon
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제4권3호
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    • pp.182-188
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    • 2004
  • We demonstrate a $2.1\;{\times}\;1.0\;{\times}\;0.1cm^3$ sized compact transmitter using LTCC System-in-Package (SiP) technology for 60GHz-band wireless communication applications. For low-attenuation characteristics and resonance suppression of the SiP, we have proposed and demonstrated a coplanar double wire-bond transition and novel CPW-to-stripline transition integrating air-cavities as well as novel air-cavities embedded CPW line. The fabricated transmitter achieves an output of 13dBm at a RF frequency of 62GHz, an IF frequency of 2.4GHz, and a LO frequency of 59.6GHz. The up-conversion gain is 11dB, while the LO signal is suppressed with the image rejection mixer below -21.4dBc, and the image and spurious signals are also suppressed below -31dBc.

FTIR study of E7 liquid crystals confined to perfluorinated carboxylic acid treated cylindrical cavities of Anodisc membranes

  • Ha, Ki-Ryong;Ahn, Hee-Jun;Yoon, Sung-Kyoun;Lee, Dong-Ho;West, John L.
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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    • pp.369-372
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    • 2004
  • Orientation of E7 liquid crystals(LCs) confined to 200 nm-diameter cylindrical cavities of Anodisc membranes are investigated by FTIR dichroism techniques. The cavity walls of the confining pores are chemically modified with different perfluorinated carboxylic acids (PCA, $C_nF_{2n+1}$COOH, n=3, 4, 5, 6). From the FTIR spectra of PCA treated alumina Anodsic membranes, we found the salt formation between -COOH group of PCA and Anodisc membrane. From the FTIR spectra of LC filled Anodisc membranes, we found abrupt alignment direction change of LC molecules between n=4 and 5 for 1 mM PCA treated Anodisc membranes, from parallel to perpendicular direction to the cavity walls. But 5mM PCA treated Anodisc membranes, alignment direction of LC molecules changed between n=3 and n=4, from parallel to perpendicular direction.

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박판 몰드를 이용한 솔더 범프 패턴의 형성 공정 (Fabrication of Solder Bump Pattern Using Thin Mold)

  • 남동진;이재학;유중돈
    • Journal of Welding and Joining
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    • 제25권2호
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    • pp.76-81
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    • 2007
  • Solder bumps have been used to interconnect the chip and substrate, and the size of the solder bump decreases below $100{\mu}m$ to accommodate higher packaging density. In order to fabricate solder bumps, a mold to chip transfer process is suggested in this work. Since the thin stainless steel mold is not wet by the solder, the molten solder is forced to fill the mold cavities with ultrasonic vibration. The solders within the mold cavities are transferred to the Cu pads on the polyimide film through reflow soldering.

핫러너 금형에서 캐비티사이의 충전불균형 현상에 관한 연구 (A Study on the Filling Imbalances between Multi-Cavity in Hot-Runner Mold)

  • 한성렬;정영득
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2005년도 춘계학술대회 논문집
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    • pp.598-601
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    • 2005
  • Plastic parts are molded for the purpose of mass production in multi-cavity system. Therefore, designer is usually designing molds that has geometrically balanced runner lay-out for filling balance at each cavities. Although, mold is manufactured with geometrically balanced runner lay-out, there are actually filling imbalances in cavities. These filling imbalances phenomenon are caused by complicated interaction between melt and mold. In this study, based on previous studies for filling imbalances in cold-runner mold, filling imbalances in hot-runner mold were investigated by CAE and injection molding experiments. ABS, PMMA as amorphous polymer and PA, PP as crystalline polymer were used to compare the filling imbalances. The filling imbalances decreased as injection rate increased without regard to kind of resins and were lower than the one of cold-runner.

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흥국사 동종의 비파괴 조사 분석 (Non-destructive Analysis of Bronze Bell in the Heungguksa Temple)

  • 홍종욱;이재진
    • 보존과학연구
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    • 통권31호
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    • pp.131-140
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    • 2010
  • This study shows the comparison of chemical compositions of main component with other bronze bells after the research on the component analysis by non-destructive XRF analysis. There are shrinkage cavities caused by the shrinkage defect and pores with pollutants on Bronze Bell of Heungguksa Temple with gamma radiation images and 77.3% of copper, 8.4% of tin and 10.9% of lead were determined as the main components of it with XRF analysis The tin content of Brozen Bell of Heungguksa Temple is less than those (11~18%) of other bronze bells but the lead content of that is higher. The lead content of it shows 10.91% which is quite high while generally the lead contents of other bells were controlled lower than 2.1%. Buddhist bells have the different lead content according to the period. The lead content was low until Silla Dynasty and Unified Silla period but it has been getting higher since some point of Koryo Dynasty. It is assumed that expensive copper and tin were replaced with lead.

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다수 캐비티에서의 균형 충전을 위한 새로운 러너 시스템 (A New Runner System for Filling Balance in the Multi-Cavities Molds)

  • 장민규;박태원;정영득
    • Design & Manufacturing
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    • 제7권1호
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    • pp.19-22
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    • 2013
  • Almost all injection molds have multi-cavity runner system for mass production, which are designed with geometrically balanced runner system in order to accomplish filling balance between cavity to cavity during processing. However, even though geometrically balanced runner is used, filling imbalances have been observed. So, many studies for improving filling balance in the multi-cavities molds are worked up. In this study, the Melt-Buffer which is a new runner system for filling balance has been suggested, and a series of experiment about degree of filling balance in cavity-to-cavity was conducted in the mold with the Melt-Buffer. From the experiment, the filling balance was increased up to 5~6% by using the Melt-Buffer.

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게이트 산화막 가장자리에 Air-cavity를 가지는 새로운 구조의 다결정 실리콘 박막 트랜지스터 (A New Poly-Si TFT Employing Air-Cavities at the Edge of Gate Oxide)

  • 이민철;정상훈;송인혁;한민구
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제50권8호
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    • pp.365-370
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    • 2001
  • We have proposed and fabricated a new poly-Si TFT employing air-cavities at the edges of gate oxide in order to reduce the vertical electric field induced near the drain due to low dielectric constant of air. Air-cavity has been successfully fabricated by employing the wet etching of gate oxide and APCVD (Atmospheric pressure chemical vapor deposition) oxide deposition. Our experimental results show that the leakage current of the proposed TFT is considerably reduced by the factor of 10 and threshold voltage shift under high gate bias is also reduced because the carrier injection into gate insulator over the drain depletion region is suppressed.

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Cu 배선의 평탄화를 위한 ECMD에 관한 연구 (Electro-chemical Mechanical Deposition for Planarization of Cu Interconnect)

  • 정석훈;서헌덕;박범영;박재홍;박성민;정문기;정해도;김형재
    • 한국전기전자재료학회논문지
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    • 제18권9호
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    • pp.793-797
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    • 2005
  • This study introduces Electro-chemical Mechanical Deposition(ECMD) lot making Cu interconnect. ECMD is a novel technique that has ability to deposit planar conductive films on non-planar substrate surfaces. Technique involves electrochemical deposition(ECD) and mechanical sweeping of the substrate surface Preferential deposition into the cavities on the substrate surface nay be achieved through two difference mechanisms. The first mechanism is more chemical and essential. It involves enhancing deposition into the cavities where mechanical sweeping does not reach. The second mechanism involves reducing deposition onto surface that is swept. In this study, we demonstrate ECMD process and characteristic. We proceeded this experiment by changing of distribution of current density on divided water area zones and use different pad types.

블크 마이크로 머신용 미세구조물의 제작 (Fabrication of 3-dimensional microstructures for bulk micromachining)

  • 최성규;남효덕;정연식;류지구;정귀상
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
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    • pp.741-744
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    • 2001
  • This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

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The Fabrication of SOB SOI Structures with Buried Cavity for Bulk Micro Machining Applications

  • Kim, Jae-Min;Lee, Jong-Chun;Chung, Gwiy-Sang
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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    • pp.739-742
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    • 2002
  • This paper described on the fabrication of microstructures by DRIE(deep reactive ion etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing($1000^{\circ}C$, 60 min.), The SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as an accurate thickness control and a good flatness.

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