• Journal of Power Electronics
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• v.17 no.1
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• pp.76-87
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• 2017

Finite-set predictive current control (FS-PCC) is advantageous for power converters due to its high dynamic performance and has received increasing interest in multilevel inverters. Among multilevel inverter topologies, the cascaded H-bridge (CHB) inverter is popular and mature in the industry. However, a main drawback of FS-PCC is its large computational burden, especially for the application of CHB inverters. In this paper, an FS-PCC method based on a deadbeat solution for three-phase zero-common-mode-voltage CHB inverters is proposed. In the proposed method, an inverse model of the load is utilized to calculate the reference voltage based on the reference current. In addition, a cost function is directly expressed in the terms of the voltage errors. An optimal control actuation is selected by minimizing the cost function. In the proposed method, only three instead of all of the control actuations are used for the calculations in one sampling period. This leads to a significant reduction in computations. The proposed method is tested on a three-phase 5-level CHB inverter. Simulation and experimental results show a very similar and comparable control performance from the proposed method compared with the traditional FS-PCC method which evaluates the cost function for all of the control actuations.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1706-1715
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• 2016

In this paper, a single phase modified switched-diode topology for both symmetrical and asymmetrical cascaded multilevel inverters is presented. It consists of a Modified Switched-Diode Unit (MSDU) and a Twin Source Two Switch Unit (TSTSU) to produce distinct positive voltage levels according to the operating modes. An additional H-bridge synthesizes a voltage waveform, where the voltage levels of either polarity have less Total Harmonic Distortion (THD). Higher-level inverters can be built by cascading MSDUs. A comparative analysis is done with other topologies. The proposed topology results in reductions in the number of power switches, losses, installation area, voltage stress and converter cost. The Nearest Level Control (NLC) technique is employed to generate the gating signals for the power switches. To verify the performance of the proposed structure, simulation results are carried out by a PSIM under both steady state and dynamic conditions. Experimental results are presented to validate the simulation results.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.5
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• pp.376-380
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• 2010

This paper presents a circuit configuration of multilevel inverter to increase the number of output voltage levels by using conventional 5-level inverters connected in series. Most of all it can maximize the number of output voltage levels by employing input voltage sources, which have the power of five. When it synthesizes the same number of output voltage levels, the proposed inverter can save the number of switching devices compared with the conventional cascaded H-bridge cell inverter. So it can reduce the size, cost, power consumption of the system. We implemented computer-aided simulation and experiments for a 25-level inverter employing two 5-level inverters.

• Journal of Power Electronics
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• v.19 no.3
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• pp.727-743
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• 2019

This paper presents a pulse-width modulation strategy to eliminate the common mode voltage (CMV) with reduced CMV spikes in multilevel inverters since a high CMV magnitude and its fast variations dv/dt result in bearing failure of motors, overvoltage at motor terminals, and electromagnetic interference (EMI). The proposed method only utilizes the zero CMV states in a space vector diagram and it is implemented by a carrier-based pulse-width modulation (CBPWM) method. This method is generalized for odd number levels of inverters including neutral-point-clamped (NPC) and cascaded H-bridge inverters. Then it is extended to the over-modulation mode. The over-modulation mode is implemented by using the two-limit trajectory principle to maintain linear control and to avoid look-up tables. Even though the CMV is eliminated, CMV spikes that can cause EMI and bearing current problems still exist due to the deadtime effect. As a result, the deadtime effect is analyzed. By taking the deadtime effect into consideration, the proposed method is capable of reducing CMV spikes. Simulation and experimental results verify the effectiveness of the proposed strategy.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.681-684
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• 2005

This paper presents a useful multilevel PWM inverter scheme based on a (3$^{n-1}$+2) level generation technique. It consists of a PWM inverter, an assembly of LEVEL inverters, and cascaded transformers. To produce high quality output voltage waves, it synthesizes a large number of output voltage levels using cascaded transformers, which have a series-connected secondary. By a suitable selection of secondary turn-ration of the transformer, the amplitude of an output voltage is appeared at the rate of an integer to an input dc source. Operational principles and analysis are illustrated in depth. The validity of the proposed system is verified through computer-aided simulations and experimental results using prototypes generation output voltages of an 11-level and a 29-level, respectively. And their results are compared with conventional counterparts.

• Journal of Power Electronics
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• v.13 no.2
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• pp.223-231
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• 2013

A modular three-phase multilevel inverter especially suitable for electrical drive applications has been previously presented. This topology is based on series connection of power cells in which each cell comprised of two inverter legs in series. In this paper, in order to generate the maximum number of voltage levels with reduced number of switches, three algorithms are proposed for determination of the magnitudes of dc voltage sources. In addition, a new hybrid multilevel inverter is proposed that is composed of series connection of the previously presented multilevel inverter and some H-bridges. The proposed topology has been compared with some other presented multilevel inverters. The performance of the proposed multilevel inverter has been verified by simulation and experimental results of a single-phase 39-level multilevel inverter.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.4
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• pp.457-463
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• 2012

Cascaded H-bridge multilevel inverters shows a useful circuit configuration to increase the number of output voltage levels to obtain high quality output voltage. By applying the concept of the power of three to dc voltage sources, it can increase the number of output voltage levels effectively. To realize this concept, two approaches may be considered. One is to use independent dc voltage sources pre-scaled in the power of three, and the other is to use instantaneous dc voltage sources generated from a cascaded transformer, which has the secondary turn-ratios scaled in the power of three in sequence. A common feature in both approaches is to use the concept of the power of three for dc voltage sources, and a point of difference is whether it adopts a low frequency transformer or not, and where the transformer is located. According to the difference, application areas are limited and show different characteristics on THD of output voltages. We compare and analyze both approaches for their circuit configurations, voltage level generating method, THD characteristics of output voltage, efficiency, application areas, limitations, and other characteristics by experiments using 500 [W] prototypes when they generate a 27-level output voltage.

• Journal of Power Electronics
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• v.1 no.1
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• pp.36-47
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• 2001

The carrier-based space vector pulse width modulation(SVPWM), which is considered as highly simple and efficient PWM technology, can be also used in multilevel inverters. The method was originally designed for the two-level inverter and developed to the diode clamped multilevel inverter structure. however it may be noted that it also cause bad switch utilization in cascaded multilevel inverter. This paper introduces an improved carrier-based SVPWM scheme, which is fully suitable for cascaded multilevel inverter topologies because it can achieve the optimized switch utilization through the redistribution of the triangular carrier waves considering leg voltage redundancies while having the advantages of the conventional carrier-based SVPWM. Using simulation and experimental results, the superior performance of new PWM method is shown.

• Journal of international Conference on Electrical Machines and Systems
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• v.2 no.2
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• pp.197-201
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• 2013

Cascaded H-bridge multilevel inverter requires independent DC voltage sources to produce multi output voltage levels. When it needs to generate more levels in the output voltage wave, the number of independent DC voltage sources usually limits its extension. To solve this problem, we propose a cascaded H-bridge multilevel inverter employing a front-end flyback converter for unifying input DC voltage sources. After theoretical analysis of the proposed circuit, we verify the validity of the proposed inverter using computer-aided simulations and experiments.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.270-279
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• 2018

This paper elucidates a hysteresis current controller for enhancing the performance of static synchronous compensator (STATCOM) using cascaded H-bridge multilevel inverter. Due to the rising power demand and growing conventional generation costs a new alternative in renewable energy source is gaining popularity and recognition. A five level single phase cascaded multilevel inverter with two separated dc sources, which is energized by photovoltaic - wind hybrid energy source. The voltages across the each dc source is balanced and standardized by the proposed hysteresis current controller. The performance of STATCOM is analyzed by connecting with grid connected system, under the steady state & dynamic state. To reduce the Total Harmonic Distortion (THD) and to improve the output voltage, closed loop hysteresis current control is achieved using PLL and PI controller. The performance of the proposed system is scrutinized through various simulation results using matlab/simulink and hardware results are also verified with simulation results.