• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.3
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• pp.43-50
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• 2010

DDC(Digital Down Converter) is a conversion technology to decimate to a lower sampling rate and DDC for the future development of communications technology has the necessary skills. So, it has been recognized in the wireless and the SDR(Software Defined Radio) system as essential components. In addition, research is underway on spectrum sensing for efficient communications environment due to the shortage of frequency resources. In this paper, the DDC systems were analyzed for CIC(Cascaded Integrator Comb) Filter, WDF(Wave Digital Filter), SRC(Sample Rate Conversion) each module. Moreover, we proposed a linkage effectively between DDC system and Spectrum Sensing for improve the efficiency of use of frequency by computer simulations. The simulation results of the DDC system was applied to the spectrum sensing capabilities. Also, performance and complexity of the results were derived and proposed system was the result of the check.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.3
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• pp.11-17
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• 2010

Multi-standard, multi-band, multi-service system to ensure a flexible interface between the SDR (Software Defined Radio) technology for the implementation of the Stability and Low-Power, Low-Calcualrion DDC (Digital Down Conversion) technology is essential. DDC technology consists of a digital channel filter. This is a typical digital filter because of the limited fisheries are vulnerable to overflow and rounding errors are drawbacks. In this paper, we overcome this disadvantage, we propose the structure of the DDC. The way WDF (Wave Digital Filter) Structural rounding error due to the structural resistance to noise. Therefore, This is the useful structure when the filter coefficients's word length is short. In addition, since IIR filters based on FIR filters based on the amount of computation is reduced because fewer than filter's tap. The proposed structure is used in DDC that CIC (Cascaded Integrator Comb) filter, WDF, IFOP (Interpolated Fourth-Order Polynomials) were analyzed with respect to, the results were confirmed by computer simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.405-408
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• 2015

While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure, which is a type of an IIR filter. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

• Journal of Satellite, Information and Communications
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• v.5 no.1
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• pp.32-37
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• 2010

The algorithm of multiple channel signal processing requires the flexibility of variable frequency band, efficient allocation of transmission power, and flexible frequency band reallocation to satisfy various service types which requires different transmission rates and frequency band. There are three methods including per-channel approach, multiple tree approach, and block approach performing frequency band reallocation method by channelization and dechannelization in the multiple-channel signal. This paper proposes an improved per-channel approach for converting the frequency band of multiple carrier signals efficiently. The proposed algorithm performs decimation and interpolation using CIC(cascaded integrator comb filter), half-band filter, and FIR filter. In addition, it performs filtering of each sub-channel, and reallocates channel band through FIR low-pass filter in the multiple-channel signal. The computer simulation result shows that the perfect reconstruction of output signal and the flexible frequency band reallocation is performed efficiently by the proposed algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2649-2655
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• 2015

While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• Journal of the Korea Society of Computer and Information
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• v.17 no.2
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• pp.113-118
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• 2012

In this paper, we discuss the design of the Digital Down Converters for the IEEE 802.11 wireless LAN receiver, which can be used for the customized receiver. The customized receiver can be used for special puropsed services which cannot be realized using the general custom chip. In the OFDM receiver, DDC receives the up sampled Inphase/Quadrature signal from the AD converter and process down sampling and filtering procedures using the Cascaded Intergrator Filter and FIR filters. We discuss the structure and design methodology of DDC's and analyze the simulation results.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.3
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• pp.2-17
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• 1999

Interpolated second order polynomials(ISOP's) are proposed to design efficient cascaded integrator-comb(CIC)-based decimation filters for a programmable downconverter. It is shown that some simple ISOP's can effectively reduce the passband droop caused by CIC filtering with little degradation in aliasing attenuation. In addition, ISOP's are shown to be useful for simplifying halfband filters that usually follow CIC filtering. As a result, a modified half band filter(MHBF) is introduced which is simpler than conventional halfband filters. The proposed decimation filter for a programmable downconverter is a cascade of a CIC filter, an ISOP, MHBF's and a programmable finite impulse response(FIR) filter. A procedure for designing the decimation filter is developed. In particular, an optimization technique that simultaneously designs the decimation filter is developed. In particular, an optimization technique that simultaneously designs the ISOP and programmable FIR filters is presented. Design examples demonstrate that the proposed method leads to more efficient programmable downconverters than existing ones.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1776-1782
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• 2010

The interferometric fiber optic gyroscopes (FOGs) are well known as sensors of rotation, which are based on Sagnac effect, and have been under development for a number of years to meet a wide range of performance requirements. This paper describes the development of open-loop FOG and digital signal processing techniques implemented on FPGA. Our primary goal was to obtain intermediate accuracy (pointing grade) with a good bias stability (0.22deg) and scale factor stability, extremely low angle random walk (0.07deg) and significant cost savings by using a single mode fiber. A secondary goal is to design all digital FOG signal processing algorithms with which the SNR at the digital demodulator output is enhanced substantially due to processing gain. The Cascaded integrator bomb(CIC) type of decimation filter only requires adders and shift registers, low cost processors which has low computing power still can used in this all digital FOG processor.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.951-954
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• 2001

본 논문에서는 SDR (Software Defined Radio)시스템을 위한 디지털 IF (Intermediate Frequency)수신기를 구현하였다[1][2]. 구현된 수신기의 하드웨어 구조는 AD변환부, PDC(Programmable Down Converter)부, DSP (Digital Signal Processing)부분으로 이루어졌다. AD변환부는 Analog Devices사의 AD6644를 이용하여 아날로그 신호를14bit의 디지털 신호로 변환된다. PDC부분은 Intersil사의 HSP 50214B를 이용하여 14bit 샘플 된 IF(Intermediate Frequency)입력을 혼합기와 NCO(Numerically Controlled Oscillator)에 의해 기저대역으로 다운 시키는 역할을 한다. PDC는 CIC (Cascaded Integrator Comb)필터, Halfband 필터 그리고 프로그램할 수 있는 FIR필터로 구성되어 있다. 그리고 PDC부분을 제어하고 PDC부분에서 처리할 수 없는 캐리어, 심볼 트래킹을 위해 Texas Instrument사의 16비트의 고정소수점 DSP인 TMS320C5416과 Altera사의 FPGA를 사용하였다. 그러므로 중간주파수 대역과 기저대역 간의 신호변환을 디지털 신호처리를 수행함으로써 일반적인 아날로그 처리방식보다 고도의 유연성과 고성능 동작이 가능하고 시간과 환경 변화에 우수한 동작 특성을 제공한다.