• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.126-134
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• 1990

In order to implement high-speed data acquistion system in CMOS VLSI technology, means must be found to overcome the relatively low transconductance and large device mismatch characteristic of MOS device. Because of these device limitations, circuit design approaches tradition-ally used in high-speed bipolar analog-to-digital converter(ADC) are suited to CMOS implementation. Also the design of VLSI CMOS comparator wherein voltage comparision is accomplished by means of a pipelined cascade RSA (Regenerative Sense Amplifier). So, in this paper we designed the A/D converter incorporates the pipelined CMOS comparator.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1146-1155
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• 2017

Normally, the artificial intelligence algorithms are widely applied to the optimal controller design. Then, it is expected that the best output performance is achieved. Unfortunately, when resulting controller parameters are implemented by using the practical devices, the output performance cannot be the best as expected. Therefore, the paper presents the optimal controller design using the combination between the state-space averaging model and the adaptive Tabu search algorithm with the new criteria as two penalty conditions to handle the mentioned problem. The buck-boost converter regulated by the cascade PI controllers is used as the example power system. The results show that the output performance is better than those from the conventional design method for both input and load variations. Moreover, it is confirmed that the reported controllers can be implemented using the realistic devices without the limitation and the stable operation is also guaranteed. The results are also validated by the simulation using the topology model of MATLAB and also experimentally verified by the testing rig.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.2
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• pp.158-165
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• 2012

In this paper, the test bed using three-phase PWM converter connected with single phase inverter in series is set up to configure an active AC electric load. Since the two topologies, three-phase PWM converter and single-phase inverter, can be operated bidirectionally, the system not only re-generates surplus power to grid but also prevents power dissipation. However, the construction of system has a drawback. That is, ripple components two times of inverter operation frequency occur at DC-Link due to cascade connection, it can be cause of three phase unbalance Since the operational characteristic of the active AC electric load, the power frequency entered into the electric load can be varied, and the ripple of DC-Link is changed as well. In this paper, the three-phase PWM converter using a variable notch filter is proposed, and the reduction of three-phase current unbalance is presented. the validity of the proposed PWM converter using a variable notch filter is verified by the simulation and experimental results.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.777-783
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• 2001

This paper is mainly concerned with the state of the practical developments of a constants PWM bridge type resonants DC-DC suitable converter for Nd:YAG Laser with a Microprocessor. (PIC16C54 & 8051) The use of IGBT power supply with feedback control of flashLamp currents imparts a advantages to Nd:YAG Laser for materials processing. these include the alility to tailor the pulseshape and modify pulse parameters on a pulse- by pulse basis. And Correct choice of pulseshape can enhance the repeatability of the process. as higher power IGBT became available, act ive pulseforming power supplies will find greater user in deep hole drilling machine By Using certain control tecniques, utililized in designing Pic16c54 from Microchip technology and Intel 8051, also Mornitoring from Microsoft Visual Basic 5, And it allowed us to designed and fabricate ahigh repel it ion rate and high power(HRHP) pulsed Nd:YAG laser system, As a result of that, the current pulsewidth could be contort led 200s to 350s(step 50s) , and the pulse repetition rate could be adjusted 500pps to 1150pps. In addition, in the case of one laser head consisting of a Nd:YAG laser rod and two flashlamps , the maximum laser output of 240w was produced at the condition of 350s and 1150pps, and that of about 480w was generated at the same condition when two laser heads were arranged in cascade.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.1
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• pp.55-62
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• 2008

This paper proposes a feedback linearization control scheme of AC/DC PWM converters with LCL input filters using no damping resisters. This feedback linearization scheme can eliminate the non-linearity of the system. So, the controller of the system can be designed by using linear control theory, which gives a good transient response. The cascade structure of the controller makes the converter current be controlled within a certain limit. To reduce the number of sensors, the source voltage and current is estimated. The validity of the proposed control algorithm is verified by simulation and experimental results.

• Journal of Power Electronics
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• v.19 no.1
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• pp.89-98
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• 2019

This paper analyzes the input side performance of a conventional three-phase to single-phase matrix converter (3-1MC). It also presents the input-side waveform quality under this topology. The suppression of low-frequency input current harmonics is studied using the 3-1MC plus capacitance compensation unit. The constraint between the modulation function of the output and compensation sides is analyzed, and the relations among the voltage utilization ratio and the output compensation capacitance, filter capacitors and other system parameters are deduced. For a 3-1MC without large-capacity energy storage, the system performance is susceptible to input voltage imbalance. This paper decouples the inner current of the 3-1MC using a Lyapunov function in the input positive and negative sequence bi-coordinate axes. Meanwhile, the outer loop adopts a voltage-weighted synthesis of the output and compensation sides as a cascade of control objects. Experiments show that this strategy suppresses the low-frequency input current harmonics caused by input voltage imbalance, and ensures that the system maintains good static and dynamic performances under input-unbalanced conditions. At the same time, the parameter selection and debugging methods are simple.

• Journal of Sensor Science and Technology
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• v.31 no.2
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• pp.115-119
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• 2022

A readout circuit for a mercury-cadmium-telluride (MCT)-amplified mid-wave infrared (IR) photodetector was realized and applied to noncontact chemical agent detectors based on a quantum cascade laser (QCL). The QCL emitted 250 times for each wavelength in 0.2-㎛ steps from 8 to 12 ㎛ with a frequency of 100 kHz and duty ratio of 10%. Because of the nonconstant QCL emission power during on-duty, averaging the photodetector signals is essential. Averaging can be performed in digital back-end processing through a high-speed analog-to-digital converter (ADC) or in analog front-end processing through an integrator circuit. In addition, it should be considered that the 250 IR data points should be completely transferred to a PC during each wavelength tuning period of the QCL. To average and minimize the IR data, we designed a readout circuit using the analog front-end processing method. The proposed readout circuit consisted of a switched-capacitor integrator, voltage level shifter, relatively low-speed analog-to-digital converter, and micro-control unit. We confirmed that the MCT photodetector signal according to the QCL source can be accurately read and transferred to the PC without omissions.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.44-45
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• 2016

본 논문에서는 DC Nano-grid를 위한 25kW급 고효율 양방향 컨버터를 개발하였다. 제안하는 양방향 컨버터는 넓은 입력전압 범위를 만족하기 위하여 Cascade 부스트-벅 컨버터의 구조로 하였으며 상용화된 SiC MosFET기반 3레그 IPM을 최적으로 사용하기 위해 2상 인터리빙 부스트 컨버터와 단상 벅 컨버터로 하였다. 또한 승 강압 모드에 따라 스위칭하는 스위치 개수를 감소시켜 스위칭 손실을 최소화 하였다. 25kW 시작품을 통해 14kW에서 효율 98.9%를 달성하였다.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.2
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• pp.80-86
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• 2003

In this paper, a new three-phase voltage-source inverter topology for high voltage and high Power applications is proposed to improve the quality of output voltage waveform. A chain converter which is used as an auxiliary circuit generates a ripple voltage and injects it to the conventional 12-step inverter. Thus, the injection of the ripple voltage results in 36-step operation with a link and 60-step operation with two links. The proposed inverter is compared to the conventional multilevel inverter in the viewpoint of ratings of phase- shifting transformers, switching devices and capacitors employed. The proposed scheme is simple to control capacitor voltages compared to the conventional schems and is cost effective for high voltage and high power application over several tens of MVA. The proposed approach is validated through simulation, and the experimental results are provided from a 2KVA laboratory prototype.