• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.811-818
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• 2016

A continuous fine-tuning phase locked loop with an additional negative feedback loop has been proposed. When the phase locked loop is out-of-lock, the phase locked loop has a fast locking characteristic using the continuous band-selection loop. When the phase locked loop is near in-lock, the bandwidth is narrowed with the fine loop. The additional negative feedback loop consists of a voltage controlled oscillator, a frequency voltage converter and its internal loop filter. It serves a negative feedback function to the main phase locked loop, and improves the phase noise characteristics and the stability of the proposed phase locked loop. The additional negative feedback loop makes the continuous fine-tuning loop work stably without any voltage fluctuation in the loop filter. Measurement results of the fabricated phase locked loop in $0.18{\mu}m$ CMOS process show that the phase noise is -109.6dBc/Hz at 2MHz offset from 742.8MHz carrier frequency.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.7
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• pp.646-652
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• 2013

EU's Galileo project is a market-based GNSS (Global Navigation Satellite System) that is under development. It is expected that Galileo will provide the positioning services based on new technologies in 2020s. Because Galileo E1 signal for OS (Open Service) shares the same center frequency with GPS L1 C/A signal, CBOC (Composite Binary Offset Carrier) modulation scheme is used in the E1 signal to guarantee interoperability between two systems. With E1 signal consisting of a data channel and a pilot channel at the same frequency band, there exist several options in designing signal acquisition for Assisted-Galileo receivers. Furthermore, compared to SNR worksheet of Assisted-GPS, some factors should be examined in Assisted-Galileo due to different correlation profile and code length of E1 signal. This paper presents SNR worksheets of Galileo E1 signals in E1-B and E1-C channel. Three implementation losses that are quite different from GPS are mainly analyzed in establishing SNR worksheets. In the worksheet, hybrid long integration of 1.5s is considered to acquire weak signal less than -150dBm. Simulation results show that the final SNR of E1-B signal with -150dBm is 19.4dB and that of E1-C signal is 25.2dB. Comparison of relative computation shows that E1-B channel is more profitable to acquire the strongest signal in weak signal environment. With information from the first satellite signal acquisition, fast acquisition of the weak signal around -155dBm can be performed with E1-C signal in the subsequent satellites.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.1 s.92
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• pp.49-55
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• 2005

In this paper, the phase locked harmonic oscillator(PLHO) using the analog PLL(Phase Locked Loop) is designed and implemented for a wireless LAN system. The harmonic oscillator is consisted of a ring resonator, a varactor diode and a PLL circuit. Because the fundamental fiequency of 8.5 GHz is used as the feedback signal for the PLL and the 2nd harmonic of 17.0 GHz is used as the output, a analog frequency divider for the phase comparison in the PLL system can be omitted. For the simple PLL circuit, the SPD(Sampling Phase Detector) as a phase comparator is used. The output power of the phase locked harmonic oscillator is 2.23 dBm at 17 GHz. The fundamental and 3rd harmonic suppressions are -31.5 dBc and -29.0 dBc, respectively. The measured phase noise characteristics are -87.6 dBc/Hz and -95.4 dBc/Hz at the of offset frequency of 1 kHz and 10 kHz from the carrier, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.49-56
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• 2006

This paper describes the design and the verification of IEEE 802.15.4 LR-WPAN 2.4GHz Physical layer for Ubiquitous Sensor Network(USN). We designed the Carrier Frequency Offset(CFO) compensation satisfied the frequency tolerance of IEEE 802.15.4 LR-WPAN and the adaptive matched filter that re-setting of the threshold for the symbol synchronization of the various USN environment. The multiplications is reduced 1/16 by this method each other at i, q phases and has 0.5dB performance improvement in detection probability. Proposed baseband system is designed with verilog HDL and implemented using FPGA prototype board.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.4
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• pp.18-26
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• 2001

In this paper, we propose an ATC(Automatic Transfer mode Controller) algorithm and an average-mode-change method for use in Gear shift PLL which can automatically change loop gain. The proposed ATC algorithm accurately detects proper timing or the mode change and has a very simpler structure - than the conventional lock detector algorithm often used in QPSK. And the proposed average mode change method can obtain low errors of estimated frequency offset by averaging the loop filter output of frequency component in shift register. These algorithms are also useful in designing ASIC, since these algorithms occupy small circuit area and are adaptable for high speed digital processing. We also present phase tracking performance of proposed Gear-shift PLL, which is composed of polarity decision PD, ATC and average mode change circuit, and analyze the results by examining constellation at each mode.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.64-72
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• 2012

Synchronization including timing recovery, frequency offset compensation, and frame synchronization is most important signal processing block in all wireless/wired communication systems. In most communication systems, synchronization schemes based on training sequences or preambles are used. WLAN standards of 802.11a/g/n released by IEEE are based on OFDM systems. OFDM systems are known to be much more sensitive to frequency and timing synchronization errors than single carrier systems. A loss of orthogonality between the multiplexed subcarriers can result in severe performance degradations. The starting position of the frame and the beginning of the symbol and training symbol can be estimated using correlation methods. Correlation processing functionality is usually complex because of large number of multipliers in implementation especially when the reference signal is non-binary. In this paper, a simple correlation based synchronization scheme is proposed for IEEE 802.11a/g/n systems. Existing property of a periodicity in the training symbols are exploited. Simulation and implementation results show that the proposed method has much smaller complexity without any performance degradation than the existing schemes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.10C
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• pp.1017-1026
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• 2005

In burst OFDM system, the frame synchronization should be performed first for the acquisition of received frame and the estimation of the correct FFT-window position. The conventional frame synchronization algorithms using design features of the preamble symbol, the repetition pattern of the OFDM symbol by pilot sub-carrier allocation rule and Cyclic Prefix(CP), has difficulty in the detection of precise frame timing because its correlation characteristics would increase and decrease gradually. Also, the algorithm based on the correlation between the reference signal and the received signal has performance degradation due to frequency offset. Therefore, we adopt a differential correlation method that is robust to frequency offset and has the clear peak value at the correct frame timing for frame synchronization. However, performance improvement is essential for differential correlation methods, since it usually shows multiple peak values due to the repetition pattern. In this paper, we propose an enhanced frame synchronization algorithm based on the differential correlation method that shows a clear single peak value by using differential correlation between samples of identical repeating pattern. We also introduce a normalization scheme which normalizes the result of differential correlation with signal power to reduce the frame timing error in the high speed mobile channel environments.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.2
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• pp.152-160
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• 2008

In this paper, we analyze the performance of a direct-conversion UHF RFID reader with the range correlation effects of the phase noise. Since a UHF RFIB system uses the same oscillator to generate the transmitted carrier and the local oscillation, the periodic interference and phase noise reduction effects occur due to time delay between two signals. Through exact theory and simulation, we verify how to cancel the periodic interference phenomena using I/Q diversity combining technique. And, we analyze phase noise reduction effects due to range correlation as a function of the tag-reader distance and the offset frequency Using these results, we simulate the symbol-error-rate performance with respect to phase noise with and without range correation effects. We show that the phase noise of the local oscillator has little effect on the symbol-error-rate performance because of phase noise reduction by range correlation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.1
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• pp.38-46
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• 2012

In this paper, we propose a decision feedback equalizer based on LDPC(Low Density Parity Check) code for the fast processing and performance improvement in OFDM system. LDPC code has good error correcting capability and its performance approaches the Shannon capacity limit. However, it has longer parity check matrix and needs more iteration numbers. In our proposed system, MSE(Mean Square Error) of signal between decision device and decoder is fed back to equalizer. This proposed system can improve BER performance because it corrects estimated channel response more accurately. In addition, the proposed system can reduce complexity because it has a lower number of iterations than system without feedback at the same performance. Simulation results evaluate and show the performance of OFDM system with the CFO and phase noise in multipath channel.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.4
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• pp.333-337
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• 2004

This paper describe a design of 5GHz OFDM baseband chip for IEEE 802.11a wireless LAN. The proposed device is consists of transmitter and receiver within a single FPGA chip. We applied single tap equalizer that use Normalized LMS algorithm to remove ISI that happen at high speed data transmission. And also, we used carrier wave frequency offset algorithm that use training symbol to remove ICI. The simulation results show the correct transmission without errors the between transmitter and receiver And we can remarkably reduce the number of register through the synthesized circuits by using DSP block and EMB(Embedded Memory Block). The target device for implementation of the synthesized circuits is Altera Stratix EPIS25FC672 FPGA and design platform is VHDL.