• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1973-1981
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• 1994

A PLDRO(Phase Locked Dielectric Resonator Oscillator) in Ku-band(10.95-11.70GHz) is designed with the concept of the feedback property of PLL(Phase Locked Loop). A series feedback type DRO is developed, and VCDRO(Voltage Controlled Dielectric Resonator Oscillator) using a varactor diode as a voltage-variable capacitor is implemented to tune oscillating frequency electrically. Then, PLDRO is designed by using a SPD(Sampling Phase Detector). This PLDRO is phase-locked voltage controlled DRO to reference source(VHF band) by SPD at 10.00 GHz for European FSS(Fixed Satellite Service). The PLDRO generates output power greater than 10dBm at 10.00 GHz and has phase noise of -80 dBc/Hz at 10 KHz offset from carrier. This PLDRO achieves much better frequency stability than conventional VCDRO.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.122-128
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• 2005

In this paper, a low noise parallel feedback oscillator for harmonic suppression and a frequency doubler are designed and implemented. As the fundamental signal of the oscillator for frequency doubling is extracted between the dielectric resonator (DR) filter and the gate device of the active device, the undesired harmonics at the output of the oscillator is remarkably suppressed. The fundamental signal of the oscillator for frequency doubling directly feeds to the frequency doubler without an additional band pass filter for harmonic suppression. The second harmonic suppression of -47.7 dBc at the oscillator output is achieved, while the fundamental suppression of -37.5 dBc at the doubler output is obtained. The phase noise characteristics are -80.3 dBc/Hz and -93.5 dBc/Hz at the offset frequency of 10 KHz and 100 KHz from the carrier, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.581-586
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• 2010

MC-DS-CDMA is technique where a single data symbol is transmitted at multiple subcarriers which are orthogonal to each other. With this technique, frequency diversity can be achieved. Time variant channels lead to interchannel interference which increases the bit error rate for MC-DS-CDMA systems. The performance of PSAM MC-DS-CDMA system over time variant channels is analyzed. The BER performance of this system over multipath fading environment is evaluated, considering the channel estimation error, carrier frequency offset.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.3 no.2 s.5
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• pp.69-74
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• 2004

In this work, A PLDRO (Phase Locked Dielectric Resonator Oscillator) which can be used for the wireless communication systems fur MMC(Microwave Micro Cell) and ITS wireless communication system is designed. A different approach to the PLDRO structure is applied for phase locking by dual phase lock loop structure. The proposed dual loop PLDRO generates the output power of 0 dBm at 18.7 GHz and has the characteristics of a phase noise of -80 dBc/Hz at 1kHz, -83 dBc/Hz at 10 kHz offset frequency from carrier frequency

• Journal of information and communication convergence engineering
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• v.16 no.1
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• pp.12-16
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• 2018

In this work, a voltage controlled oscillator (VCO) monolithic microwave integrated circuit (MMIC) was demonstrated for 10-GHz band motion detecting sensors. The VCO MMIC was fabricated using a $2-{\mu}m$ InGap/GaAs HBT process, and the tuning of the oscillation frequency is achieved by changing the internal capacitance in the HBT, instead of using extra varactor diodes. The implemented VCO MMIC has a micro size of $500{\mu}m{\times}500{\mu}m$, and demonstrates the value of inserting the VCO into a single chip transceiver. The experimental results showed that the frequency tuning characteristic was above 30 MHz, with the excellent output flatness characteristic of ${\pm}0.2dBm$ over the tuning bandwidth. And, the VCO MMIC exhibited a phase noise characteristic of -92.64 dBc/Hz and -118.28 dBc/Hz at the 100 kHz and 1 MHz offset frequencies from the carrier, respectively. The measured values were consistent with the design values, and exhibited good performance.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.66-75
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• 1997

We derive the system design parameters to implement the receiving system for the PCS mobile station to satisfy the J-sTD-018 which is the PCS mobile station(MS) minimum performance. Also we analyze the system performance and intermodulation spurious due to the values of a device cause the system performance degradation, is proposed. The simulation shows the receiver's maximum system noise figure to satisfy the receiver selectivity is approximately 11 dB. While the MS noise figure is 10dB with system margin 1 dB, the minimum selectivity is -71 dB at 1.25MHz frequency offset from the carrier frequency. And the input 3rd order intercept point of the MS class I and the MS class II~V is -9.5 dBm and -14dBm respectively. When the interference power level at the receiver is small, the receiver has better performance as we increase the gain of the LNA. However, when the interference level at the receiver is large, the receiver performance is heavily affected by the spurious as we increase the gain of the LNA. Thus, we proved the effectiveness of the LNA On/Off switching technique as to reduce the effect of the spurious.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.234-238
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• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a $0.25-{\mu}m$ standard CMOS Process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier, Total power dissipation is 7.5 mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.6
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• pp.816-824
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• 1999

Design and performance of 18 GHz phase locked dielectric resonator oscillator(PLDRO) for Point-to-point radio link using analog phase locked loop is described which achieve high stability and low SSB phase noise. The module consists of an 18 GHz voltage controlled dielectric resonator oscillator(VCDRO), buffered amplifier, analog phase detector which are integrated to form a miniature hybrid circuit. In addition, containing a low phase noise VHF PLL has been designed to lock any other conventional N times frequency of crystal oscillator. The module achieves stable phase locked state, exhibits output power of 21 dBm at 18.00 GHz, -34 dBc harmonic suppression and -75 dBc/Hz phase noise at 10 kHz offset frequency from carrier.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.32-36
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• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a 0.25-$\mu\textrm{m}$ standard CMOS process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier. Total power dissipation is 7.5 mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.307-310
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• 2001

In this paper we describe the design and implementation of uplink receiver for BWLL base station modem. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we use Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.1