• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.16-24
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• 2009

In this paper, DC-DC buck converter with on-chip filter inductor and capacitor is presented. By operating at high switching frequency of 50MHz with stacked interleaved topology, we reduced inductor and capacitor sizes compared to previously published DC-DC buck converters. The proposed circuit is designed in a standard $0.5{\mu}m$ CMOS process, and chip area is $9mm^2$. This circuit operated at the input voltage of $3{\sim}5V$ range, the maximum load current of 250mA, and the maximum efficiency of 71%.

• Journal of Power Electronics
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• v.14 no.1
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• pp.30-39
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• 2014

This paper studies a new three-level pulse-width modulation (PWM) resonant converter for high input voltage and high load current applications. In order to use high frequency power MOSFETs for high input voltage applications, a three-level DC converter with two clamped diodes and a flying capacitor is adopted in the proposed circuit. For high load current applications, the secondary sides of the proposed converter are connected in parallel to reduce the size of the magnetic core and copper windings and to decrease the current rating of the rectifier diodes. In order to share the load current and reduce the switch counts, three resonant converters with the same active switches are adopted in the proposed circuit. Two transformers with a series connection in the primary side and a parallel connection in the secondary side are adopted in each converter to balance the secondary side currents. To overcome the drawback of a wide range of switching frequencies in conventional series resonant converters, the duty cycle control is adopted in the proposed circuit to achieve zero current switching (ZCS) turn-off for the rectifier diodes and zero voltage switching (ZVS) turn-on for the active switches. Finally, experimental results are provided to verify the effectiveness of the proposed converter.

• Proceedings of the KIPE Conference
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• 2001.12a
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• pp.105-108
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• 2001

This paper compared a Modified C-dump converter and energy efficient converter topologies, derived from the conventional C-dump converter, for switched reluctance motor (SRM) drives. The proposed topologies overcome the limitations of the conventional C-dump converter, and could reduce the whole cost of the SRM drive. Also, the above converters have simple control requirements; and allow the motor phase current to freewheel during chopping mode. Specially, the voltage ratings of the dump capacitor and some of the switching devices in the proposed an Energy efficient C-dump converter is reduced to the supply voltage ($V_{dc}$) level compared to twice the supply voltage ($2V_{dc}$) in the conventional C-dump converter. Simulation and experimental results of the proposed converters are presented and verified.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.8
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• pp.1046-1054
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• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability. The developed hardware prototype can be utilized for analyzing the basic operation and performance improvement of MMC according to the modulation and redundancy operation scheme. It also can be utilize to analyze the basic operational characteristics of HVDC system based on MMC.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1480-1488
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• 2015

In this paper, a revolutionary buck converter is proposed with soft-switching technology, which is realized by a coupled inductor. Both zero-voltage switching (ZVS) of main switch and zero-current switching (ZCS) of freewheeling diode are achieved at turn on and turn off without using any auxiliary circuits by the resonance between the parasitic capacitor and the coupled inductor. Furthermore, the peak voltages of the main switch and the peak current of the freewheeling diode are significantly reduced by the coupled inductor. As a result, the proposed converter has the advantages of simple circuit, convenient control, low consumption and so on. The detailed operation principles and steady-state analysis of the proposed ZVS-ZCS buck converter are presented, and detailed power loss analysis and some simulation results are also included. Finally, experimental results based on a 200-W prototype are provided to verify the theory and design of the proposed converter.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.688-698
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• 2018

Quasi Z-Source Multilevel Inverter (QZMLI) topology has attracted grid connected Photovoltaic (PV) systems in recent days. So there is a remarkable research thrust in switching techniques and control strategies of QZMLI. This paper presents the mathematical analysis of Phase shift- Pulse Width Amplitude Modulation (PS-PWAM) for QZMLI and emphasizes on the advantages of the technique. The proposed technique uses the maximum and minimum envelopes of the reference waves for generation of pulses and proportion of it to generate shoot-through pulses. Hence, it results in maximum utilization of input voltage, lesser switching loss, reduced Total Harmonic Distortion (THD) of the output voltage, reduced inductor current ripple and capacitor voltage ripple. Due to these qualities, the QZMLI with PS-PWAM emerges to be the best suitable for PV based grid connected applications compared to Phase shift-Pulse Width Modulation (PS-PWM). The detailed math analysis of the proposed technique has been disclosed. Simulation has been performed for the proposed technique using MATLAB/Simulink. A prototype has been built to validate the results for which the pulses were generated using FPGA /SPARTAN 3E.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.10
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• pp.506-510
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• 2002

In this paper, we study on the mutual characteristics between transmitting efficiency of pulse energy and wall plug consumed power of non-thermal Plasma for removing environmental pollutive gas of coal plant. To obtain high pulse energy of our system, we used MPC(magnetic pulse compressor) of power switch and tested their characteristics by adjusting electrode length of reactor and charging voltage in capacitor. As a result, we obtained consumed power of wall plug and a compressed pulse of voltage 110kV, rising time 500ns. Impedance of load on increasing electrode length was decreased, but electrical efficiency was increased. These results indicate we can control critical voltage of pulse corona and electrical efficiency of economic cost in power plant.

• Journal of Power Electronics
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• v.13 no.3
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• pp.469-478
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• 2013

This paper proposes a novel scheme for the current controller for the grid-side converter (GSC) of permanent-magnet synchronous generator (PMSG) wind turbines to eliminate the high-order harmonics in the grid currents under grid voltage disturbances. The voltage unbalance and harmonics in three-phase systems cause grid current distortions. In order to mitigate the input current distortions, multi-loop current controllers are applied, where the positive-sequence component is regulated by proportional-integral (PI) controllers, and the negative-sequence and high-order harmonic components are regulated by proportional-resonance (PR) controllers. For extracting the positive/negative-sequence and harmonic components of the grid voltages and currents without a phase delay or magnitude reduction, composite observers are applied, which give faster and more precise estimation results. In addition, an active damping method using PR controllers to damp the grid current component of the resonant frequency is employed to improve the operating stability of VSCs with inductor-capacitor-inductor (LCL) filters. The validity of the proposed method is verified by simulation and experimental results.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.9
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• pp.60-66
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• 2014

In case of DC railway, value of ESS(Energy Storage System) is already approved. Whereas AC railway system, there are a lot of differences such as system design and operation pattern. Therefore there is doubt about AC ESS usefulness. Especially, regenerative energy can return to the source. So in case of AC 25kV system, it is necessary to consider different operation algorithm compare to DC railway system. In this paper ESS which is installed in AC high-speed railway was introduced. Power consumption pattern of High speed trains were analyzed, proper storage material was reviewed and operation algorithm was suggested. Super capacitor and Battery was used with hybrid type. Super capacitor was used to handle short term energy movement because of its prompt response and battery was used to handle long term energy movement because of its high energy density. Also in case of operation algorithm, phase control method was upgraded compare to voltage magnitude detection method.